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參數資料
| 型號： | TSC2008TRGVRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC16 |
| 封裝： | 4 X 4 MM, PLASTIC, VQFN-16 |
| 文件頁數： | 19/35頁 |
| 文件大小： | 418K |
| 代理商： | TSC2008TRGVRQ1 |
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1
SCLK
CS
8
1
SDO
PENIRQ
S
SDI
ControlBits
S
ControlBits
HIGH: Disableor(EnableandNotTouched)
New
Definition
PENIRQ
LOW: EnableandTouched
7
6
5
7
6
5
4
3
2
1
0
8
1
8
A2 A1 A0 MODE
SER/
DFR
PD1 PD0
A2 A1 A0 MODE
SER/
DFR
PD1 PD0
n
n +1
n
n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle
Acquire Conv
Idle
Acquire Conv
Idle
New
Def
PENIRQ
1
SCLK
CS
8
1
SDO
PENIRQ
S
SDI
ControlBits
S
1
ControlBits
HIGH: Disableor(EnableandNotTouched)
LOW: EnableandTouched
7
6
5
7
6
5
4
3
2
1
0
8
1
A2 A1 A0 MODE
SER/
DFR
PD1 PD0
A2 A1 A0 MODE
SER/
DFR
PD1 PD0
n
n +1
n
n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle
Acquire Conv
Idle
Acquire
Conv
Idle
SBAS552
– JUNE 2011
8-BIT OPERATION TIMING
If the 8-bit ADC mode produces an acceptable result, then 16 SCLKs per cycle operation can also be used, as
shown in Figure 33. If SDO is released one-half SCLK cycle earlier (with the SDO adjusted option), the fastest
transfer (eight SCLKs per cycle) is achievable; see Figure 34.
Figure 33. Conversion Timing
—8-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, without Adjusted
SDO Timing (TSC2046-Compatible)
Figure 34. Conversion Timing
—8-Bit Mode, 8 SCLKs per Cycle, 8-Bit Bus Interface, with Adjusted SDO
Timing
26
Copyright
2011, Texas Instruments Incorporated
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