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參數資料
| 型號： | TSC2008TRGVRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC16 |
| 封裝： | 4 X 4 MM, PLASTIC, VQFN-16 |
| 文件頁數： | 33/35頁 |
| 文件大小： | 418K |
| 代理商： | TSC2008TRGVRQ1 |
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SBAS552
– JUNE 2011
TIMING REQUIREMENTS
(1)
All specifications typical at
–40°C to +105°C, VDD = 1.6V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1.2V
≤ VDD < 1.6V, 40% to 60% duty cycle
182
ns
tC(SCLK)
SPI serial clock cycle time
1.6
≤ VDD < 2.7V, 40% to 60% duty cycle
62.5
ns
2.7V
≤ VDD ≤ 3.6V, 40% to 60% duty cycle
40
ns
1.2V
≤ VDD < 1.6V, 10pF load
5.5
MHz
fSCLK
SPI serial clock frequency
1.6
≤ VDD < 2.7V, 10pF load
16
MHz
2.7V
≤ VDD ≤ 3.6V, 10pF load
25
MHz
tWH(SCLK)
SPI serial clock high time
0.4
× tC(SCLK)
0.6
× tC(SCLK)
ns
tWL(SCLK)
SPI serial clock low time
0.4
× tC(SCLK)
0.6
× tC(SCLK)
ns
1.2V
≤ VDD < 1.6V
22
ns
tSU(CSF-SCLK1R)
Enable lead time
1.6
≤ VDD < 3.6V
14
ns
1.2V
≤ VDD < 1.6V
55
ns
tD(CSF-SDOVALID)
Slave access time
1.6
≤ VDD < 3.6V
25
ns
1.2V
≤ VDD < 1.6V
40
80
ns
tH(SCLKF-SDOVALID)
MISO data hold time
1.6
≤ VDD < 3.6V
6
30
ns
1.2V
≤ VDD < 1.6V
50
ns
tWH(CS)
Sequential transfer delay
1.6
≤ VDD < 3.6V
20
ns
1.2V
≤ VDD < 1.6V
25
ns
tSU(SDI-SCLKR)
MOSI data setup time
1.6
≤ VDD < 3.6V
10
ns
tH(SDI-SCLKR)
MOSI data hold time
5
ns
1.2V
≤ VDD < 1.6V
55
ns
tDIS(CSR-SDOZ)
Slave MISO disable time
1.6
≤ VDD < 3.6V
25
ns
1.2V
≤ VDD < 1.6V
50
ns
tSU(SCLKF-CSR)
Enable lag time
1.6
≤ VDD < 3.6V
20
ns
1.2V
≤ VDD < 1.6V
55
ns
PENIRQ (used as BUSY)
tD(SCLKR-PENIRQF)
delay from SCLK rising edge 1.6 ≤ VDD < 3.6V
25
ns
Setup time from PENIRQ
1.2V
≤ VDD < 1.6V
50
ns
tSU(PENIRQR-SCLKR)
(used as BUSY) to the rising
1.6
≤ VDD < 3.6V
20
ns
edge of SCLK
tD(RESET)
Reset period requirement
200
ns
tR
Rise time
VDD = 3V, fSCLK = 25MHz
3
ns
tF
Fall time
VDD = 3V, fSCLK = 25MHz
3
ns
(1)
All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Copyright
2011, Texas Instruments Incorporated
7
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