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參數資料
| 型號： | UAA3580 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Wideband code division multiple access frequency division duplex zero IF receiver |
| 中文描述： | 寬帶碼分多址頻分雙工零中頻接收機 |
| 文件頁數： | 11/24頁 |
| 文件大小： | 107K |
| 代理商： | UAA3580 |
2002 Oct 30
11
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
9.3
RF PLL synthesizer
The RF fractional-N synthesizer is set via the 3-wire bus
with the FRAC and CH chains. CH sets the integer divider
ratio and FRAC the fractional divider ratio. They both
provide the LO frequency in accordance with the following
equation:
N
2
22
Where
Where K
RX
is the integer value of FRAC[21:0], N
RX
is the
integer value of CH[8:0] and f
ref
is the external frequency
reference applied to pin REFIN.
Example
: to obtain a f
RFLO
frequency of 2.14 GHz with an
error less than
f
PLL
N
RX
must be set to 164 and K
frac(RX)
to 1290555 if the reference frequency is 26 MHz. It should
be noted that some particular frequencies can be obtained
in two ways; N
RX
= x and K
frac(RX)
= 0.25 provides the
same frequency as N
RX
= x
1 and K
frac(RX)
= 0.75
9.4
Clock PLL synthesizer
9.4.1
AFC
MODE
The clock PLL is based on the SD fractional-N synthesizer
thatallowstoderivetheUMTSsystemclockincludingAFC
from a non-corrected external 26 MHz only GMS
reference. The clock PLL frequency with the AFC
correction word is given by the following equation:
9
K
+
2
512
2
21
Where
AFC represents the integer value of AFC[11:0] and f
ref
is
the external reference frequency applied to pin REFIN.
9.4.2
C
LOCK
PLL
MODES
The clock PLL synthesizer is controlled by bits CLKon and
CLKoff. At power-up the clock PLL synthesizer is
automatically on when pin RXCEN is set HIGH. The
control, done with CLKon, will be reset at the rising edge
of RXCEN. For application which do not require the UMTS
clock system, the clock PLL can be powered-down with bit
CLKoff set to logic 1.
Table 4
Clock mode
Notes
1.
2.
Hard power-down of the clock PLL done with RXCEN.
Power-down achieved via the 3-wire bus, reset by
RXCEN.
Power-down achieved via the 3-wire bus, no effect by
RXCEN in this mode. This mode will be reset if V
DDD
is not maintained.
X = don’t care.
3.
4.
9.4.3
C
LOCK
PLL
OUTPUT DIVIDER
The clock PLL output divider ratio is set in accordance with
Table 5.
Table 5
Clock mode; note 1
Note
1.
X = don’t care.
f
RFLO
f
ref
----2
K
frac(RX)
+
×
=
K
frac(RX)
-1
K
RX
1
2
+
×
=
f
CLKPLL
f
ref
-----------------------
×
=
K
AFC
231
AFC
+
=
RXCEN CLKon CLKoff
DESCRIPTION
1
1
0
CLKPLL synthesizer
enabled (default)
CLKPLL synthesizer
disabled; note 1
CLKPLL synthesizer
disabled; note 2
CLKPLL synthesizer
disabled; note 3
0
1
0
1
0
0
X
(4)
X
(4)
1
CLKoff
CLK1
CLK0
DESCRIPTION
1
X
X
UMTSCLKO output
disabled
clock divider ratio set to
default
clock divider ratio set to 2
clock divider ratio set to 4
clock divider ratio set to 8
0
0
0
0
0
0
0
1
1
1
0
1
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