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參數(shù)資料
| 型號： | UAA3580 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Wideband code division multiple access frequency division duplex zero IF receiver |
| 中文描述： | 寬帶碼分多址頻分雙工零中頻接收機 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 107K |
| 代理商： | UAA3580 |
2002 Oct 30
14
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
13 DC CHARACTERISTICS
V
CCA
= 2.6 V; V
CCA(CP)
= 2.6 V;T
amb
= 25
°
C; unless otherwise specified.
Notes
1.
2.
3.
4.
5.
6.
Receive mode: All circuits are active.
Receive mode: All circuits are active with the clock PLL off (CLKoff = 1).
Synthesizer mode: RF PLL and clock PLL are active.
Standby mode: Clock PLL is active.
Sleep mode: RXCEN set LOW, DATA, CLK and EN are in high-impedance.
Receive mode: DC voltage supplied from the IC.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CCA
analog supply voltage
on pins V
CCA(RF)
, V
CCA(IF)
,
V
CCA(CP)
and V
CCA(SYN)
2.6
2.8
3.3
V
V
DDD
I
CCA(tot)
digital supply voltage
total analog supply current
1.6
1.8
52
45
25
12
10
19
2.8
63
54
30
15
50
V
mA
mA
mA
mA
μ
A
mA
receive mode; note 1
receive mode; note 2
synthesizer mode; note 3
standby mode; note 4
sleep mode; note 5
I
CCA(RF)
analog supply current for the RF
VCO section
analog supply current for the RX
section
analog supply current for the
synthesizer
analog supply current for the
charge pump
digital supply current
I
CCA(IF)
16
mA
I
CCA(SYN)
15
mA
I
CCA(CP)
0.9
mA
I
DDD
Baseband IQ section; pins IN, IP, QP and QN
1.1
mA
V
O(IQ)(CM)
IQ common mode output voltage
0.5(V
IN
+ V
IP
) or
0.5(V
QP
+ V
QN
); note 6
1.15
1.25
1.35
V
RF VCO section; pin CAPVCOREG
V
O(CAPVCOREG)
CLKPLL section; pin UMTSCLKO
output voltage
2
V
V
O(UMTSCLKO)
Reference voltage; pin REXT
output voltage
0.8
V
V
REXT
reference voltage for the charge
pump
R
ext
= 1.8 k
360
mV
Control section; pins DATA, CLK, EN and RXON
V
IH
V
IL
HIGH-level input voltage
LOW-level input voltage
0.9
0.3
V
V
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