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參數資料
| 型號： | UAA3580 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Wideband code division multiple access frequency division duplex zero IF receiver |
| 中文描述： | 寬帶碼分多址頻分雙工零中頻接收機 |
| 文件頁數： | 12/24頁 |
| 文件大小： | 107K |
| 代理商： | UAA3580 |
2002 Oct 30
12
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
10 PROGRAMMING
10.1
Serial programming bus
Asimple3-wireunidirectionalserialbusisusedtoprogram
the circuit. The 3 lines are DATA, CLK and EN.
The data sent to the device is loaded in bursts framed
by EN. Programming clock edges are ignored until EN
goes active LOW. The programmed information is loaded
into the addressed latch when EN goes HIGH (inactive).
This is allowed when CLK is in either state without causing
any consequences to the data register. Only the last
21 bits serially clocked into the device are retained within
the programming register. Additional leading bits are
ignored, and no check is made on the number of clock
pulses.
The fully static CMOS design uses virtually no current
when the bus is inactive. It can always capture new
programming data even during Power-down of the
synthesizer.
10.2
Data format
Data is entered with the most significant bit first. The
leading bits make up the data field, while the trailing four
bits are an address field. The address bits are decoded on
the rising edge of EN. This produces an internal load pulse
to store the data in the address latch.
To ensure that data is correctly loaded on first power-up,
EN should be held LOW and only taken HIGH after having
programmed an appropriate register. To avoid erroneous
divider ratios, the pulse is inhibited during the period when
data is read by the frequency dividers. This condition is
guaranteed by respecting a minimum EN pulse width after
data transfer.
10.3
Register contents
Table 6
Register bit allocation
Table 7
Description of symbols used in Table 6
CONTROL BITS
ADDRESS
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address
for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address
FRAC[15:0]
CH[8:0]
0
0
0
0
0
AGC[8:0]
0
AFC[11:0]
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
SYNON
SYNON
RXON
CLKon
FR[21:16]
1
1
CLKoff
1
CKO[1:0]
SYMBOL
BITS
DESCRIPTION
SYNON
RXON
AGC
CH
FRAC
AFC
CLKoff
CKO
1
1
9
6
22
12
1
2
3-wire bus
3-wire bus
automatic gain control
integer division ratio for the RF PLL
fractional division ratio for the RF PLL
automatic frequency control for the clock PLL
clock PLL disabled
integer division ratio for the clock PLL
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