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參數資料
| 型號： | UAA3580 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Wideband code division multiple access frequency division duplex zero IF receiver |
| 中文描述： | 寬帶碼分多址頻分雙工零中頻接收機 |
| 文件頁數： | 8/24頁 |
| 文件大小： | 107K |
| 代理商： | UAA3580 |
2002 Oct 30
8
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
9
OPERATING MODES
9.1
Basic operating modes
The circuit can be powered up into different operating
modes, depending on the control bits RXON and SYNON,
via the 3-wire bus. This defines three main modes called
IDLE, SYN and RX mode.
The voltage level applied to pin RXCEN must be set HIGH
to enable the device. The VCO and the PLL sections are
enabled in SYN mode. In the RX mode every section is
enabled (receive part, VCO and PLL sections).
Table 2
Selection of operating mode
9.2
AGC gain look-up table
The AGC gain is set via the AGC[8:0] bits; see Table 3.
MODE
SYNON
RXON
IDLE
SYN
RX
0
1
1
0
0
1
Table 3
AGC gain look-up table
AGC8
AGC7
AGC6
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
ATTENUATION FROM
MAXIMUM GAIN (dB)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
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