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參數資料
| 型號： | UAA3580 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Wideband code division multiple access frequency division duplex zero IF receiver |
| 中文描述： | 寬帶碼分多址頻分雙工零中頻接收機 |
| 文件頁數： | 17/24頁 |
| 文件大小： | 107K |
| 代理商： | UAA3580 |
2002 Oct 30
17
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
Fractional-N synthesizer;
where
N
K
AFC
Integrated CLKPLL VCO; pin CPCLKO
integer divider ratio
fractional divider ratio
0.4512
9
0.4532
f
VCO
G
VCO
V
tune
Output CLKPLL buffer; pin UMTSCLKO
CLKPLL frequency
VCO gain
tuning voltage
V
CPCLKO
= 0 to 3.3 V
V
CPCLKO
= 1.3 V
100
12
0.4
15
140
23
V
CCA
0.4
MHz
MHz/V
V
f
UMTSCLKO
N
Φ
n
frequency range
divider ratio
close-in-phase noise
15.36
2
30.72
4
61.44
8
90
MHz
at 2 kHz offset for
30.72 MHz
at 3.84 MHz offset for
30.72 MHz
R
L
= 10 k
dBc/Hz
phase noise
110
dBc/Hz
V
o(p-p)
output voltage (peak-to-peak
value)
1
V
Low noise crystal amplifier; pin REFIN
f
REF
V
i(REF)(rms)
R
i(REF)
C
i(REF)
reference frequency
input voltage (RMS value)
input resistance
input capacitance
13
50
tbf
tbf
26
400
MHz
mV
k
pF
f
REF
= 26 MHz
f
REF
= 26 MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
CLKPLL
f
ref
N
------------------------
K
2
×
=
K
AFC
512
2
21
AFC
+
=
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