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參數資料
| 型號： | XC2S50-5TQG144C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 18/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPARTAN-II FPGA 50K 144-TQFP |
| 標準包裝： | 60 |
| 系列： | Spartan®-II |
| LAB/CLB數： | 384 |
| 邏輯元件/單元數： | 1728 |
| RAM 位總計： | 32768 |
| 輸入/輸出數： | 92 |
| 門數： | 50000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 產品目錄頁面： | 599 (CN2011-ZH PDF) |
| 其它名稱： | 122-1321 |
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Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
25
R
If CCLK is slower than FCCNH, the FPGA will never assert
BUSY. In this case, the above handshake is unnecessary,
and data can simply be entered into the FPGA every CCLK
cycle.
A configuration packet does not have to be written in one
continuous stretch, rather it can be split into many write
sequences. Each sequence would involve assertion of CS.
In applications where multiple clock cycles may be required
to access the configuration data before each byte can be
loaded into the Slave Parallel interface, a new byte of data
may not be ready for each consecutive CCLK edge. In such
a case the CS signal may be de-asserted until the next byte
is valid on D0-D7. While CS is High, the Slave Parallel
interface does not expect any data and ignores all CCLK
transitions. However, to avoid aborting configuration,
WRITE must continue to be asserted while CS is asserted.
Abort
To abort configuration during a write sequence, de-assert
WRITE while holding CS Low. The abort operation is
initiated at the rising edge of CCLK, as shown in Figure 21,
page 26. The device will remain BUSY until the aborted
operation is complete. After aborting configuration, data is
assumed to be unaligned to word boundaries and the FPGA
requires a new synchronization word prior to accepting any
new packets.
Boundary-Scan Mode
In the boundary-scan mode, no nondedicated pins are
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port.
Configuration through the TAP uses the special CFG_IN
instruction. This instruction allows data input on TDI to be
converted into data packets for the internal configuration
bus.
The following steps are required to configure the FPGA
through the boundary-scan port.
1.
Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
2.
Enter the Shift-DR (SDR) state
3.
Shift a standard configuration bitstream into TDI
4.
Return to Run-Test-Idle (RTI)
5.
Load the JSTART instruction into IR
6.
Enter the SDR state
7.
Clock TCK through the sequence (the length is
programmable)
8.
Return to RTI
Configuration and readback via the TAP is always available.
The boundary-scan mode simply locks out the other modes.
The boundary-scan mode is selected by a <10x> on the
mode pins (M0, M1, M2).
Readback
The configuration data stored in the Spartan-II FPGA
configuration memory can be readback for verification.
Along with the configuration data it is possible to readback
the contents of all flip-flops/latches, LUT RAMs, and block
RAMs. This capability is used for real-time debugging.
For more detailed information see XAPP176, Spartan-II
FPGA Family Configuration and Readback.
Figure 19: Loading Configuration Data for the Slave
Parallel Mode
Yes
No
FPGA
Driving BUSY
High?
After INIT
Goes High
Load One
Configuration
Byte on Next
CCLK Rising Edge
To CRC Check
DS001_19_032300
No
End of
Configuration
Data File?
Yes
User Drives
WRITE and CS
Low
User Drives
WRITE and CS
High
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XC2S50-5TQG144I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 50K GATES 1728 CELLS 263MHZ 2.5V 144TQFP EP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XC2S50-5VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S50-5VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S50-5VQG100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S50-5VQG100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
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