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參數(shù)資料
型號(hào)： XC2S50-5TQG144C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 9/99頁(yè)
文件大小： 0K
描述： IC SPARTAN-II FPGA 50K 144-TQFP
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-II
LAB/CLB數(shù)： 384
邏輯元件/單元數(shù)： 1728
RAM 位總計(jì)： 32768
輸入/輸出數(shù)： 92
門(mén)數(shù)： 50000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
產(chǎn)品目錄頁(yè)面： 599 (CN2011-ZH PDF)
其它名稱： 122-1321
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
17
R
Configuration
Configuration is the process by which the bitstream of a
design, as generated by the Xilinx software, is loaded into
the internal configuration memory of the FPGA. Spartan-II
devices support both serial configuration, using the
master/slave serial and JTAG modes, as well as byte-wide
configuration employing the Slave Parallel mode.
Configuration File
Spartan-II devices are configured by sequentially loading
frames of data that have been concatenated into a
configuration file. Table 8 shows how much nonvolatile
storage space is needed for Spartan-II devices.
It is important to note that, while a PROM is commonly used
to store configuration data before loading them into the
FPGA, it is by no means required. Any of a number of
different kinds of under populated nonvolatile storage
already available either on or off the board (i.e., hard drives,
FLASH cards, etc.) can be used. For more information on
configuration without a PROM, refer to XAPP098, The
Low-Cost, Efficient Serial Configuration of Spartan FPGAs.
Modes
Spartan-II devices support the following four configuration
modes:
Slave Serial mode
Master Serial mode
Slave Parallel mode
Boundary-scan mode
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
the end of configuration. The selection codes are listed in
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
Table 8: Spartan-II Configuration File Size
Device
Configuration File Size (Bits)
XC2S15
197,696
XC2S30
336,768
XC2S50
559,200
XC2S100
781,216
XC2S150
1,040,096
XC2S200
1,335,840
Table 9: Configuration Modes
Configuration Mode
Preconfiguration
Pull-ups
M0M1M2
CCLK
Direction
Data Width
Serial DOUT
Master Serial mode
No
0
Out
1
Yes
001
Slave Parallel mode
Yes
0
1
0
In
8
No
011
Boundary-Scan mode
Yes
1
0
N/A
1
No
101
Slave Serial mode
Yes
1
0
In
1
Yes
No
111
Notes:
1.
During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os
(those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration
2.
If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode
pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine
whether the unused I/Os have a pull-up, pull-down, or no resistor.
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參數(shù)描述
XC2S50-5TQG144I 制造商:Xilinx 功能描述:FPGA SPARTAN-II 50K GATES 1728 CELLS 263MHZ 2.5V 144TQFP EP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE
XC2S50-5VQ100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S50-5VQ100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S50-5VQG100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S50-5VQG100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
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