- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄21990 > XC2S50-5TQG144C (Xilinx Inc)IC SPARTAN-II FPGA 50K 144-TQFP PDF資料下載
參數(shù)資料
| 型號： | XC2S50-5TQG144C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 47/99頁 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-II FPGA 50K 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 384 |
| 邏輯元件/單元數(shù)： | 1728 |
| RAM 位總計： | 32768 |
| 輸入/輸出數(shù)： | 92 |
| 門數(shù)： | 50000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 產(chǎn)品目錄頁面： | 599 (CN2011-ZH PDF) |
| 其它名稱： | 122-1321 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
51
2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
Definition of Terms
In this document, some specifications may be designated as Advance or Preliminary. These terms are defined as follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values
are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All limits are representative of worst-case supply voltage and junction
temperature conditions. Typical numbers are based on measurements taken at a nominal VCCINT level of 2.5V and a junction
temperature of 25°C. The parameters included are common to popular designs and typical applications. All specifications
are subject to change without notice.
DC Specifications
Absolute Maximum Ratings(1)
68
Spartan-II FPGA Family:
DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Product Specification
R
Symbol
Description
Min
Max
Units
VCCINT
Supply voltage relative to GND(2)
–0.5
3.0
V
VCCO
Supply voltage relative to GND(2)
–0.5
4.0
V
VREF
Input reference voltage
–0.5
3.6
V
VIN
Input voltage relative to GND(3)
5V tolerant I/O(4)
–0.5
5.5
V
No 5V tolerance(5)
–0.5
VCCO +0.5
V
VTS
Voltage applied to 3-state output
5V tolerant I/O (4)
–0.5
5.5
V
No 5V tolerance(5)
–0.5
VCCO +0.5
V
TSTG
Storage temperature (ambient)
–65
+150
°C
TJ
Junction temperature
-
+125
°C
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2.
Power supplies may turn on in any order.
3.
VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day).
4.
Spartan-II device I/Os are 5V Tolerant whenever the LVTTL, LVCMOS2, or PCI33_5 signal standard has been selected. With 5V
Tolerant I/Os selected, the Maximum DC overshoot must be limited to either +5.5V or 10 mA, and undershoot must be limited to
either –0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot
to –2.0V or overshoot to +7.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
5.
Without 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must
be limited to –0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may
undershoot to –2.0V or overshoot to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no
greater than 100 mA.
6.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B6T-CX | CONVERTER MOD DC/DC 6.5V 75W |
| VI-27N-CW-F4 | CONVERTER MOD DC/DC 18.5V 100W |
| DS1631UT/T&R | IC DIGITAL THERM HI PREC 8MSOP |
| VI-B6R-CX | CONVERTER MOD DC/DC 7.5V 75W |
| VI-B6M-CX | CONVERTER MOD DC/DC 10V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S50-5TQG144I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 50K GATES 1728 CELLS 263MHZ 2.5V 144TQFP EP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XC2S50-5VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S50-5VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S50-5VQG100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S50-5VQG100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。