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參數(shù)資料
型號(hào): AD7707BR
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC
中文描述: 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20
封裝: 0.300 INCH, SOIC-20
文件頁(yè)數(shù): 18/40頁(yè)
文件大小: 316K
代理商: AD7707BR
REV. A
AD7707
–18–
CALIBRATION SEQUENCES
The AD7707 contains a number of calibration options as previously outlined. Table XV summarizes the calibration types, the opera-
tions involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to moni-
tor when
DRDY
returns low at the end of the sequence.
DRDY
not only indicates when the sequence is complete, but also that the
part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the calibra-
tion sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the Setup
Register. When these bits return to 0 (0 following a calibration command), it indicates that the calibration sequence is complete.
This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier indication
than
DRDY
that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0 00 represents the dura-
tion of the calibration carried out). The sequence to when
DRDY
goes low also includes a normal conversion and a pipeline delay,
t
P
, to correctly scale the results of this first conversion. t
P
will never exceed 2000
×
t
CLKIN
. The time for both methods is given in the
table.
Table XV. Calibration Sequences
Calibration Type
MD1, MD0
Calibration Sequence
Duration to Mode Bits
Duration to
9
×
1/Output Rate + t
P
DRDY
Self-Calibration
0, 1
Internal ZS Cal @ Selected Gain +
Internal FS Cal @ Selected Gain
ZS Cal on AIN @ Selected Gain
FS Cal on AIN @ Selected Gain
6
×
1/Output Rate
ZS System Calibration
FS System Calibration
1, 0
1, 1
3
×
1/Output Rate
3
×
1/Output Rate
4
×
1/Output Rate + t
P
4
×
1/Output Rate + t
P
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