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參數(shù)資料
| 型號(hào)： | AD7723 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 16位，120 MSPS的的CMOS，Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 11/23頁(yè) |
| 文件大小： | 435K |
| 代理商： | AD7723 |
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AD7723
–11–
REV. 0
SERIAL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
CFMT/
RD
4
Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid
on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on
the falling edge of the serial clock, SCO. If CFMT is logic high, SDO is valid on the rising edge of
SCO.
Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO
pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic
level equals the level on the TSI pin the serial data output, SDO, is active. Otherwise SDO will be
high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO.
In normal operations, TSI and DOE should be tied low.
Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO
signal for Serial Mode 1. A logic low makes the FSO output a pulse, one SCO cycle wide at the
beginning of a serial data transmission. With SFMT set to a logic high, the FSO signal is a frame
pulse that is active low for the duration of the 16-bit transmission. For Serial Modes 2 and 3, SFMT
should be tied high.
Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output
data register to an external source and to allow more than one AD7723, operated from a common
master clock, to simultaneously sample its analog input and update its output register.
Serial Clock Output.
Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial
Mode 1 data transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for
the remaining 16 SCO cycles. Serial Modes 2 and 3 data transmissions last 16 SCO cycles.
Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depend-
ing on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately one
SCO period wide, or a frame pulse which is active low for the duration of the 16-data bit transmission.
Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set
logic high, DOE will enable the SDO output buffer when it is a logic high, and vice versa. TSI is
used when two AD7723s are connected to the same serial data bus. When this function is not
needed, TSI and DOE should be tied low.
Serial Mode Low Pass/Band Pass Filter Select Input. With SLP set logic high, the low-pass filter
response is selected. A logic low selects band pass.
Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate
is selected. A logic low selects the high data rate. The high data rate corresponds to data at the out-
put of the fourth decimation filter (Decimate by 16). The low data rate corresponds to data at the
output of the fifth decimation filter (Decimate by 32).
Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is
equal to the CLKIN frequency. A logic high sets it equal to one-half the CLKIN frequency.
Tie to DV
DD
.
Tie to DGND.
Tie to DGND.
Tie to DGND.
Tie to DGND.
Tie to DGND.
Tie to DGND.
Tie to DGND.
DOE/DB4
43
SFMT/DB5
42
FSI/DB6
41
SCO/DB7
SDO/DB8
40
38
FSO/DB9
37
TSI/DB10
36
SLP/DB11
35
SLDR/DB12
34
SCR/DB13
33
DV
DD
/
CS
DGND/DB14
DGND/DB15
DGND/
DRDY
DGND/DB0
DGND/DB1
DGND/DB2
DGND/DB3
30
32
31
5
3
2
1
44
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| AD7723BSZ1 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7723BSZ-REEL | 功能描述:IC ADC 16BIT SIGMA-DELTA 44MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極 |
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