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參數資料
| 型號： | AD7723 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 16位，120 MSPS的的CMOS，Σ-Δ模數轉換器 |
| 文件頁數： | 17/23頁 |
| 文件大小： | 435K |
| 代理商： | AD7723 |
AD7723
–17–
REV. 0
APPLYING THE AD7723
Analog Input Range
The AD7723 has differential inputs to provide common-mode
noise rejection. In unipolar mode the analog input range is 0 to
8/5
×
V
REF2
, while in bipolar mode the analog input range is
±
4/5
×
V
REF2
. The output code is twos complement binary in
both modes with 1 LSB = 61
μ
V. The ideal input/output trans-
fer characteristics for the two modes are shown in Figure 28
below. In both modes the absolute voltage on each input must
remain within the supply range AGND to AV
DD
. The bipolar
mode allows either single-ended or complementary input
signals.
011…111
011…110
000…010
000…001
000…000
111…111
111…110
100…000
100…001
–4/5
3
V
REF2
(0V)
0V
+4/5
3
V
REF2
– 1LSB BIPOLAR
(+4/5
3
V
REF2
)
(+8/5
3
V
REF2
– 1LSB) UNIPOLAR
Figure 28. Bipolar (Unipolar) Mode Transfer Function
The AD7723 will accept full-scale inband signals, however,
large scale out of band signals can overload the modulator in-
puts. Figure 29 shows the maximum input signal level as a func-
tion of frequency. A minimal single-pole RC antialias filter set
to f
CLKIN
/24 will allow full-scale input signals over the entire
frequency spectrum.
INPUT SIGNAL FREQUENCY RELATIVE TO f
CLKIN
0
0.5
0.02
0.04
0.06
0.08
0.10
0.12
0.14
2.200
2.100
1.300
P
1.700
1.600
1.500
1.400
1.900
1.800
2.000
V
REF
= 2.5V
Figure 29. Peak Input Signal Level vs. Signal Frequency
Analog Input
The analog input of the AD7723 uses a switched capacitor
technique to sample the input signal. For the purpose of driving
the AD7723, an equivalent circuit of the analog inputs is shown
in Figure 30. For each half clock cycle, two highly linear sam-
pling capacitors are switched to both inputs, converting the
input signal into an equivalent sampled charge. A signal source
driving the analog inputs must be able to source this charge,
while also settling to the required accuracy by the end of each
half-clock phase.
500
V
500
V
AD7723
CLKIN
VIN(+)
VIN(–)
AC
GROUND
2pF
2pF
F
A
F
B
F
A
F
B
F
A
F
B
F
A
F
B
Figure 30. Analog Input Equivalent Circuit
Driving the Analog Inputs
To interface the signal source to the AD7723, at least one op
amp will generally be required. Choice of op amp will be critical
to achieving the full performance of the AD7723. The op amp
not only has to recover from the transient loads that the ADC
imposes on it, but must also have good distortion characteristics
and very low input noise. Resistors in the signal path will also
add to the overall thermal noise floor, necessitating the choice of
low value resistors.
Placing an RC filter between the drive source and the ADC
inputs, as shown in Figure 31, has a number of beneficial af-
fects: transients on the op amp outputs are significantly reduced
since the external capacitor now supplies the instantaneous
charge required when the sampling capacitors are switched to
the ADC input pins and, input circuit noise at the sample im-
ages is now significantly attenuated resulting in improved over-
all SNR. The external resistor serves to isolate the external
capacitor from the ADC output, thus improving op amp stabil-
ity while also isolating the op amp output from any remaining
transients on the capacitor. By experimenting with different
filter values, the optimum performance can be achieved for each
application. As a guideline, the RC time constant (R
×
C)
should be less than a quarter of the clock period to avoid non-
linear currents from the ADC inputs being stored on the exter-
nal capacitor and degrading distortion. This restriction means
that this filter cannot form the main antialias filter for the ADC.
VIN(+)
VIN(–)
AD7723
R
R
C
Figure 31. Input RC Network
With the unipolar input mode selected, just one op amp is re-
quired to buffer single ended input signals. However, driving
the AD7723 with complementary signals and with the bipolar
input range selected has some distinct advantages: even order
harmonics in both the drive circuits and the AD7723 front end
are attenuated; and the peak to peak input signal range on both
inputs is halved. Halving the input signal range allows some op
amps to be powered from the same supplies as the AD7723.
Although a complementary driver will require the use of two op
amps per ADC, it may avoid the need to generate additional
supplies just for these op amps.
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