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參數(shù)資料
| 型號(hào)： | AD7723 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 16位，120 MSPS的的CMOS，Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 9/23頁(yè) |
| 文件大小： | 435K |
| 代理商： | AD7723 |
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AD7723
–9–
REV. 0
PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
AV
DD1
AGND1
AV
DD
AGND
AGND2
DV
DD
DGND
REF1
11
9, 10
17, 26
16, 18, 25
22
39
6, 28
21
Digital Logic Power Supply Voltage for the Analog Modulator.
Digital Logic Power Supply Ground for the Analog Modulator.
Positive Power Supply Voltage for the Analog Modulator.
Power Supply Ground for the Analog Modulator.
Power Supply Ground Return to the Reference Circuitry, REF2, of the Analog Modulator.
Digital Power Supply Voltage; +5 V
±
5%.
Ground Reference for Digital Circuitry.
Reference Output. REF1 connects through 3 k
to the output of the internal 2.5 V reference and to
a buffer amplifier that drives the
Σ
modulator.
Reference Input. REF2 connects to the output of an internal buffer amplifier that drives the
Σ
modulator. When REF2 is used as an input, REF1 must be connected to AGND to disable the inter-
nal buffer amplifier.
Positive Terminal of the Differential Analog Input.
Negative Terminal of the Differential Analog Input.
Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar or unipo-
lar operation. A logic high input selects unipolar operation and a logic low selects bipolar operation.
Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high.
Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 M
resistor can
be connected between the XTAL pin and the CLKIN pin with XTAL_OFF tied low. External
capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal
manufacturer’s recommendation for the load capacitors.
Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL should be tied to AGND1.
Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an exter-
nal clock source. Set low when using an external crystal between the CLKIN and XTAL pins.
Mode Control Inputs. The MODE1 and MODE2 pins choose either parallel or serial data interface
operation and select the operating mode for the digital filter in parallel mode. Refer to Tables I and II.
When set high, the power dissipation is reduced by approximately one-half and a maximum CLKIN
frequency of 10 MHz applies.
Synchronization Logic Input. When using more than one AD7723, operated from a common master
clock, SYNC allows each ADC to simultaneously sample its analog input and update its output
register. A rising edge resets the AD7723 digital filter sequencer counter to zero. When the rising
edge of CLKIN senses a logic low on SYNC, the reset state is released. Because the digital filter and
sequencer are completely reset during this action, SYNC pulses cannot be applied continuously.
Standby Logic Input. A logic high sets the AD7723 into the power-down state.
REF2
23
VIN(+)
VIN(–)
UNI
20
19
24
CLKIN
12
XTAL
XTAL_OFF
13
14
MODE1/2
8, 7
HALF_PWR
15
SYNC
29
STBY
27
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