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參數(shù)資料
| 型號： | AD7723 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 16位，120 MSPS的的CMOS，Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 435K |
| 代理商： | AD7723 |
AD7723
–4–
REV. 0
(AV
DD
= DV
DD
= +5 V
6
5%; AGND = AGND1 = DGND = 0 V; f
CLKIN
= 19.2 MHz; C
L
= 50 pF; SFMT =
Logic Low or High, CFMT = Logic Low or High; T
A
= T
MIN
to T
MAX
unless otherwise noted)
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
CLKIN Frequency
CLKIN Period (t
CLK
= 1/f
CLK
)
CLKIN Low Pulsewidth
CLKIN High Pulsewidth
CLKIN Rise Time
CLKIN Fall Time
F
CLK
t
1
t
2
t
3
t
4
t
5
1
0.052
0.45
×
t
1
0.45
×
t
1
5
5
19.2
1
0.55
×
t
1
0.55
×
t
1
MHz
μ
s
ns
ns
FSI Setup Time
FSI Hold Time
FSI High Time
1
CLKIN to SCO Delay
SCO Period
2
, SCR = 1
SCO Period
2
, SCR = 0
SCO Transition to FSO High Delay
SCO Transition to FSO Low Delay
SCO Transition to SDO Valid Delay
SCO Transition from FSI
3
SDO Enable Delay Time
SDO Disable Delay Time
t
6
t
7
t
8
t
9
t
10
t
10
t
11
t
12
t
13
t
14
t
15
t
16
0
0
5
5
1
40
ns
ns
t
CLK
ns
t
CLK
t
CLK
ns
ns
ns
25
2
1
0
0
5
60
5
5
5
5
12
t
CLK
+ t
2
20
20
ns
ns
DRDY
High Time
2
Conversion Time
2
(Refer to Tables I and II)
CLKIN to
DRDY
Transition
CLKIN to DATA Valid
CS
/
RD
Setup Time to CLKIN
CS
/
RD
Hold Time to CLKIN
Data Access Time
Bus Relinquish Time
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
2
16/32
t
CLK
t
CLK
ns
ns
ns
ns
ns
ns
35
20
50
35
0
20
20
20
35
35
SYNC Input Pulsewidth
SYNC Low Time before CLKIN Rising
DRDY
High Delay after Rising SYNC
DRDY
Low Delay after SYNC Low
t
25
t
26
t
27
t
28
1
0
t
CLK
ns
ns
t
CLK
25
35
2049
NOTES
1
FSO pulses are gated by the release of FSI (going low).
2
Guaranteed by design.
3
Frame Sync is initiated on the falling edge of CLKIN.
Specifications subject to change without notice.
I
1.6mA
+1.6V
C
L
50pF
TO
OUTPUT
PIN
I
200
m
A
Figure 1. Load Circuit for Timing Specifications
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