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參數資料
| 型號： | AD7723 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 16位，120 MSPS的的CMOS，Σ-Δ模數轉換器 |
| 文件頁數： | 2/23頁 |
| 文件大小： | 435K |
| 代理商： | AD7723 |
–2–
REV. 0
AD7723–SPECIFICATIONS
1
B Version
Typ
Parameter
Test Conditions/Comments
Min
Max
Units
DYNAMIC SPECIFICATIONS
2, 3
HALF_PWR = 0 or 1
f
CLKIN
= 10 MHz When HALF-PWR = 1
Decimate by 32
Bipolar Mode
Signal to Noise
Full Power
2.5 V Reference
3 V Reference
87
88.5
86.5
90
91
89
–96
dB
dB
dB
dB
dB
dB
Half Power
Total Harmonic Distortion
4
Spurious Free Dynamic Range
4
–90
–92
–90
2.5 V Reference
3 V Reference
Unipolar Mode
Signal to Noise
Total Harmonic Distortion
4
Spurious Free Dynamic Range
4
Bandpass Filter Mode
Bipolar Mode
Signal to Noise
Decimate by 16
Bipolar Mode
Signal to Noise
87
–89
–90
dB
dB
dB
76
79
dB
Measurement Bandwidth = 0.383
×
F
O
2.5 V Reference
3 V Reference
Measurement Bandwidth = 0.5
×
F
O
2.5 V Reference
3 V Reference
2.5 V Reference
3 V Reference
82
83
78
86
87
81.5
dB
dB
dB
dB
dB
dB
dB
Signal to Noise
Total Harmonic Distortion
4
–88
–86
–90
–88
Spurious Free Dynamic Range
4
Unipolar Mode
Signal to Noise
Signal to Noise
Total Harmonic Distortion
4
Measurement Bandwidth = 0.383
×
F
O
Measurement Bandwidth = 0.5
×
F
O
84
81
–89
dB
dB
dB
DIGITAL FILTER RESPONSE
Low Pass Decimate by 32
0 kHz to f
CLKIN
/83.5
f
CLKIN
/66.9
f
CLKIN
/64
f
CLKIN
/51.9 to f
CLKIN
/2
Group Delay
Settling Time
Low Pass Decimate by 16
0 kHz to f
CLKIN
/41.75
f
CLKIN
/33.45
f
CLKIN
/32
f
CLKIN
/25.95 to f
CLKIN
/2
Group Delay
Settling Time
Band Pass Decimate by 32
f
CLKIN
/51.90 to f
CLKIN
/41.75
f
CLKIN
/62.95, f
CLKIN
/33.34
f
CLKIN
/64, f
CLKIN
/32
0 kHz to f
CLKIN
/83.5, f
CLKIN
/25.95 to f
CLKIN
/2
Group Delay
Settling Time
Output Data Rate, F
O
Decimate by 32
Decimate by 16
±
0.001
dB
dB
dB
dB
–3
–6
–90
1293/2f
CLKIN
1293/f
CLKIN
±
0.001
dB
dB
dB
dB
–3
–6
–90
541/2f
CLKIN
541/f
CLKIN
±
0.001
dB
dB
dB
dB
–3
–6
–90
1293/2f
CLKIN
1293/f
CLKIN
f
CLKIN
/32
f
CLKIN
/16
ANALOG INPUTS
Full-Scale Input Span
Bipolar Mode
Unipolar Mode
VIN(+) – VIN(–)
±
4/5
×
V
REF2
8/5
×
V
REF2
V
V
0
(AV
DD
= DV
DD
= +5 V
6
5%; AGND = AGND1 = AGND2 = DGND = 0 V;
f
CLKIN
= 19.2 MHz; REF2 = 2.5 V; T
A
= T
MIN
to T
MAX
; unless otherwise noted)
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