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參數資料
| 型號： | AD7760BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2.5 MSPS, 20-Bit ADC |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, QCC48 |
| 封裝： | LFCSP-48 |
| 文件頁數： | 13/22頁 |
| 文件大小： | 868K |
| 代理商： | AD7760BCP |
Preliminary Technical Data
AD7760
AD7760 INTERFACE
Rev. PrN | Page 13 of 22
Reading Data
The AD7760 uses a 16-bit bi-directional parallel interface. This
interface is controlled by the RD/WR and CS pins. There are
two read operating modes depending on the output data rate.
When the AD7760 is outputting data at 5MSPS or less, the
interface operates in a conventional mode as shown in Figure 2.
When a new conversion result is available, an active low pulse is
output on the DRDY pin. To read a conversion result from the
AD7760, two 16-bit read operations are performed. The DRDY
pulse indicates that a new conversion result is available. Both
RD/WR and CS go low to perform the first read operation.
Shortly after both these lines go low, the databus becomes active
and the 16 Most Significant Bits (MSBs) of the conversion result
are output. The RD/WR and CS lines must return high for a
period of TBD ns before the second read is performed. This
second read will contain the 8 Least Significant Bits (LSBs) of
the conversion result along with 7 status bits. These status bits
are shown in Table 6. The Cal bit is set to a 1 if a calibration has
been performed. Table 14 contains descriptions of the other
status bits.
Table 6. Status Bits During Data Read
D7
DValid
Ovr
UFilt
D0
0
LPwr
FiltOk
DLOk
Cal
Shortly after RD/WR and CS return high, the databus will
return to a high impedance state. Both read operations must be
completed before a new conversion result is available as the new
result will overwrite the contents on the output register. If a
DRDY pulse occurs during a read operation, the data read will
be invalid.
When the AD7760 is operating in modulator data output mode,
i.e. Output Data Rate at 20MHz, a different interfacing scheme
is necessary. To obtain data from the AD7760 in this mode, both
RD/WR and CS lines must be held low. This will bring the
databus out of its high impedance state. Figure 3 shows the
20MHz Output Data Rate operation. A DRDY pulse is
generated for each word and the data is valid on the rising edge
of the DRDY pulse. This DRDY pulse could be used to latch the
modulator data into a FIFO or as a DMA control signal. Shortly
after the RD/WR and CS lines return high, the AD7760 will
stop outputting data and the databus will return to high
impedance.
Sharing The Parallel Bus
By its nature, the high accuracy of the AD7760 make it sensitive
to external noise sources. These include digital activity on the
parallel bus. For this reason it is recommended that the AD7760
data lines are isolated from the system databus by means of a
latch or buffer to ensure that there is no digital activity on the
D0-D15 pins that is not controlled by the AD7760. If multiple,
synchronized, AD7760 parts that share a properly distributed
common MCLK signal exist in a system, these parts can share a
common bus without being isolated from each other. This bus
can then be isolated from the system bus by a single latch or
buffer.
Writing To The AD7760
After a reset, only a single write operation to power up the
AD7760 is necessary to start the part converting on default
settings. While the AD7760 is configured to convert analog
signals with the default settings on reset, there are many features
and parameters on this part that the user can change by writing
to the device. As some of the programmable registers are 16 bits
wide, to program a register requires two write operations. The
first write contains the register address while the second write
contains the register data. There is an exception to this when a
user filter is being downloaded to the AD7760. This is dealt
with in detail in the following section. The AD7760 Registers
section contains the register addresses and further details.
Figure 4 shows a write operation to the AD7760. The RD/WR
line is held high while the CS line is brought low for a minimum
of TBD ns. The register address is latched during this period.
The CS line is brought high again for a minimum of TBD ns
before the register data is put onto the databus. If a read
operation occurs between the writing of the register address
and the register data, the register address is cleared and the next
write must be the register address again. This also provides a
method to get back to a known situation if the user somehow
loses track whether the next write is an address or data.
It is envisaged that the AD7760 will be written to and
configured on power-up and very infrequently, if at all, after
that. Following any write operation, the full group delay of the
filter must pass before valid data will be output from the
AD7760.
Reading Status and Other Registers
The AD7760 features a number of programmable registers. To
read back the contents of these registers or the status register,
the user must first write to the control register of the device
setting a bit corresponding to the register they wish to read. The
next read operation will then output the contents of the selected
register instead of a conversion result. More information on the
relevant bits in the control register is given in the AD7760
Registers section.
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