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| 型號： | AD7760BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2.5 MSPS, 20-Bit ADC |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, QCC48 |
| 封裝： | LFCSP-48 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 868K |
| 代理商： | AD7760BCP |
AD7760
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Rev. PrN | Page 8 of 22
D
D
D
D
D
D
A
A
AGND
AVDD2
AVDD2
AGND
DB12
DB13
DB14
DB15
VDRIVE
DGND
DGND
DVDD
/WR
39
38
37
41
40
DGND
AGND
AVDD1
36
35
34
33
42
43
44
45
46
47
48
17 18 19 20 21 22 23 24
R
A
V
V
V
V
A
A
V
V
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
64 63 62 61 60 59 58
V
D
D
D
D
D
D
D
D
D
D
D
PIN 1
TOP VIEW
(Not to Scale)
AD7760
DGND
MCLK
AVDD2
AGND
AVDD1
AGND
DECAP1
REFGND
VREF+
AGND
AVDD4
14
15
16
25 26 27
31
30
29
28
32
57 56 55 54 53 52 51 50 49
Figure 5. 64-Lead TQFP Pin Configuration
DB15
VDRIVE
AD7760
TOP VIEW
(Not to Scale)
VDRIVE
MCLK
AVDD2
AVDD1
REFGND
AVDD4
AVDD2
AVDD2
A
A
AVDD1
/WR
DVDD
DB14
DB13
DB12
D
D
D
D
D
D
D
D
D
D
D
D
Figure 6. 48-PIN LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TQFP Pin
Number
Number
6, 33
5, 25
CSP Pin
Pin Mnemonic
Description
AV
DD1
+2.5V power supply for modulator. These pins should be decoupled to AGND with 100nF and
10μF capacitors on each pin.
+5V power supply. These pins should be decoupled to AGND with TBD nF and TBD μF
capacitors on each pin.
+3.3V to +5V power supply for differential amplifier. These pins should be decoupled to AGND
with a 100nF capacitor.
+3.3V to +5V power supply for reference buffer. This pin should be decoupled to AGND with a
10nF capacitor in series with a 22
resistor.
Power supply ground for analog circuitry. In the Chip Scale package, most of the internal
AGND pads are down-bonded to the exposed paddle. This paddle then become the main
analog ground connection for the AD7760.
4, 14, 15,
27
24
4, 10, 11,
20
17
AV
DD2
AV
DD3
12
9
AV
DD4
5, 7, 11,
13, 16, 18,
23, 28, 31,
32, 34
9
41
23, 24,
Paddle
AGND
7
31
REFGND
DV
DD
Reference Ground. Ground connection for the reference voltage.
+2.5V power supply for digital circuitry and FIR filter. This pin should be decoupled to DGND
with a 470nF capacitor.
Logic power supply input, +1.8V to +2.5V. The voltage supplied at these pins will determine
the operating voltage of the logic interface. Both these pins must be connected together and
tied to the same supply. Each pin should also be decoupled to DGND with a 470nF capacitor.
Ground Reference for digital circuitry. In the Chip Scale package, all the internal DGND pads
are down-bonded to the exposed paddle. This paddle then becomes the single ground
connection for the AD7760.
44, 63
1, 32
V
DRIVE
1, 35, 42,
43, 53, 62,
64
Paddle
DGND
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