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參數資料
型號: AD9824
廠商: Analog Devices, Inc.
英文描述: Complete 14-Bit 30 MSPS CCD Signal Processor
中文描述: 完整的14位30 MSPS的CCD信號處理器
文件頁數: 12/24頁
文件大?。?/td> 438K
代理商: AD9824
REV. 0
AD9824
–12–
0101...
0101...
0101...
*
0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
2323...
2323...
2323...
HD
LINE 0
LINE 1
LINE 2
LINE M
LINE M–1
LINE 0
LINE 1
LINE 2
LINE M
LINE M–1
EVEN FIELD
ODD FIELD
VD
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA
GAIN
GAIN0
GAIN1
GAIN0
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323... (ODD).
GAIN3
GAIN2
GAINX
GAINX
3ns MIN
VD
3ns MIN
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
FRAME N
VD
LINE 0
LINE 1
LINE 2
LINE M
0101...
1212...
0101...
LINE M–1
LINE 0
LINE 1
LINE 2
LINE M
0101...
1212...
0101...
LINE M–1
*
0 = GAIN0, 1 = GAIN1, 2 = GAIN2
FRAME N+1
HD
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
SHP
HD
PxGA
GAIN
GAIN0
GAIN1
GAIN0
NOTES
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
GAIN2
GAINX
GAINX
GAIN1
3ns MIN
VD
3ns MIN
5 PIXEL MIN
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
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