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參數資料
| 型號： | AD9824 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit 30 MSPS CCD Signal Processor |
| 中文描述： | 完整的14位30 MSPS的CCD信號處理器 |
| 文件頁數： | 19/24頁 |
| 文件大?。?/td> | 438K |
| 代理商： | AD9824 |
REV. 0
AD9824
–19–
A/D Converter
The AD9824 uses high performance ADC architecture, opti-
mized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB, as shown in
TPC 2. Instead of the 1 V full-scale range used by the earlier
AD9801 and AD9803 products from Analog Devices, the
AD9824’s ADC uses a 2 V input range. Better noise perfor-
mance results from using a larger ADC full-scale range
(see TPC 3).
AUX1 Mode
For applications that do not require CDS, the AD9824 can be
configured to sample ac-coupled waveforms. Figure 30 shows
the circuit configuration for using the AUX1 channel input
(Pin 36). A single 0.1
μ
F ac-coupling capacitor is needed between
the input signal driver and the AUX1IN pin. An on-chip dc-bias
circuit sets the average value of the input signal to approximately
0.4 V, which is referenced to the midscale code of the ADC.
The VGA Gain Register provides a gain range of 0 dB to 36 dB in
this mode of operation (see VGA Gain Curve, Figure 29).
The VGA gains up the signal level with respect to the 0.4 V bias
level. Signal levels above the bias level will be further increased
to a higher ADC code, while signal levels below the bias level
will be further decreased to a lower ADC code.
AUX2 Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 31 shows the circuit
configuration for using the AUX2 channel input (Pin 34). An
external 0.1
μ
F blocking capacitor is used with the on-chip video
clamp circuit to level shift the input signal to a desired refer-
ence level. The clamp circuit automatically senses the most
negative portion of the input signal and adjusts the voltage
across the input capacitor. This forces the black level of the
input signal to be equal to the value programmed into the Clamp
Level Register (see Serial Interface Timing and Internal Register
Description). The VGA provides gain adjustment from 0 dB to
18 dB. The same VGA Gain Register is used, but only the
9 MSBs of the gain register are used (see Table VII.)
AUX1IN
0.1 F
VGA GAIN
REGISTER
ADC
VGA
10
5k
0.4V
0.4V
INPUT SIGNAL
V
0.8V
0.4V
MIDSCALE
0dB TO 36dB
Figure 30. AUX1 Circuit Configuration
0dB TO 18dB
8
AUX2IN
BUFFER
0.1 F
VIDEO
SIGNAL
9
CLAMP LEVEL
LPF
VGA GAIN
REGISTER
ADC
VGA
VIDEO CLAMP
CIRCUIT
CLAMP LEVEL
REGISTER
Figure 31. AUX2 Circuit Configuration
Table VII. VGA Gain Register Used for AUX2-Mode
MSB
D9
LSB
D0
D10
D8
D7
D6
D5
D4
D3
D2
D1
Gain (dB)
X
0
1
X
0
X
0
X
0
X
0
1
X
0
X
0
X
0
X
0
X
0
0.0
0.0
18.0
1
1
1
1
1
1
1
1
1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9824KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 3.3V 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC 14-BIT SIGNAL PROCESSOR |
| AD9824KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 3.3V 48-Pin LFCSP EP T/R |
| AD9824KCPZ | 功能描述:IC CCD SIGNAL PROC 14BIT 48LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9824KCPZ | 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
| AD9824KCPZRL | 功能描述:IC CCD SIGNAL PROC 14BIT 48LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
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