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參數資料
| 型號： | AD9824 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit 30 MSPS CCD Signal Processor |
| 中文描述： | 完整的14位30 MSPS的CCD信號處理器 |
| 文件頁數： | 14/24頁 |
| 文件大小： | 438K |
| 代理商： | AD9824 |
REV. 0
AD9824
–14–
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. Internal Register Map
Register
Name
Address
A0 A1 A2
Data Bits
D4
D0 D1 D2
D3
D5
D6
D7
D8
D9
D10
Operation
0 0 0
Channel Select Power-Down
CCD/AUX1/2
Software
Reset
OB Clamp
On/Off
0
1
1
2
0
1
0
1
0
1
Modes
VGA Gain
1 0 0
LSB
MSB
X
Clamp Level
0 1 0
LSB
MSB
X
X
X
Control
1 1 0
Color Steering Mode
Selection
PxGA
On/Off
Clock Polarity Select for
SHP/SHD/CLP/DATA
0
1
0
1
Three-
State
X
PxGA
Gain0
0 0 1
LSB
MSB
X
X
X
X
X
PxGA
Gain1
1 0 1
LSB
MSB
X
X
X
X
X
PxGA
Gain2
0 1 1
LSB
MSB
X
X
X
X
X
PxGA
Gain3
1 1 1
LSB
MSB
X
X
X
X
X
NOTES
1
Internal use only. Must be set to zero.
2
Must be set to one.
SDATA
SCK
SL
RNW
TEST BIT
0
A2
0
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
t
DS
t
DH
t
LS
t
LH
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT-WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 21. Serial Write Operation
SDATA
SCK
SL
RNW
TEST BIT
1
0
0
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
t
DS
t
DH
t
LS
t
LH
NOTES
1. RNW = READ-NOT-WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE AND IS UPDATED ON
SCK FALLING EDGES.
t
DV
Figure 22. Serial Readback Operation
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相關代理商/技術參數 |
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