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參數資料
| 型號： | AD9851 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 180 MHz DDS/DAC Synthesizer |
| 中文描述： | 180MHz的CMOS/DAC頻率合成器 |
| 文件頁數： | 10/23頁 |
| 文件大小： | 277K |
| 代理商： | AD9851 |
AD9851
–10–
REV. 0
Table I. 8-Bit Parallel-Load Data/Control Word Functional Assignment
Word
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
W0
Phase–b4 (MSB)
Phase–b3
Phase–b2
Phase–b1
Phase–b0 (LSB)
Power-Down
Logic 0*
6
×
REFCLK
Multiplier
Enable
Freq–b24
Freq–b16
Freq–b8
Freq–b0 (LSB)
W1
W2
W3
W4
Freq–b31 (MSB)
Freq–b23
Freq–b15
Freq–b7
Freq–b30
Freq–b22
Freq–b14
Freq–b6
Freq–b29
Freq–b21
Freq–b13
Freq–b5
Freq–b28
Freq–b20
Freq–b12
Freq–b4
Freq–b27
Freq–b19
Freq–b11
Freq–b3
Freq–b26
Freq–b18
Freq–b10
Freq–b2
Freq–b25
Freq–b17
Freq–b9
Freq–b1
*This bit is always Logic 0 unless invoking the serial mode (see Figure 17). After serial mode is entered, this data bit must be set back to Logic 0 for proper operation.
W0*
W1
W2
W3
W4
t
CD
t
DH
t
DS
t
WL
t
WH
t
FD
t
FH
t
FL
*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD
AND IS ASYNCHRONOUS WITH REFERENCE CLOCK
t
CF
VALID DATA
SYSCLK
DATA
W CLK
FQ UD
A
OUT
Figure 13. Parallel-Load Frequency/Phase Update Timing Sequence
Note: To update W0 it is not necessary to load W1 through W4. Simply load W0 and assert FQ_UD. To update W1, reload W0
then W1 . . . users do not have random access to programming words.
Table II. Timing Specifications
Symbol
Definition
Min
t
DS
t
DH
t
WH
t
WL
t
CD
t
FH
t
FL
t
FD
t
CF
Data Setup Time
Data Hold Time
W_CLK High
W_CLK Low
REFCLK Delay after FQ_UD
FQ_UD High
FQ_UD Low
FQ_UD Delay after W_CLK
Output Latency from FQ_UD
Frequency Change
Phase Change
3.5 ns
3.5 ns
3.5 ns
3.5 ns
3.5 ns*
7.0 ns
7.0 ns
7.0 ns
18 SYSCLK Cycles
13 SYSCLK Cycles
*Specification does not apply when the 6
×
REFCLK Multiplier is engaged.
The function assignments of the data and control words are
shown in Tables I and III; the detailed timing sequence for
updating the output frequency and/or phase, resetting the de-
vice, engaging the 6
×
REFCLK Multiplier, and powering up/
down, are shown in the timing diagrams of Figures 13–20. As a
programming example for the following DDS characteristics:
1. Phase set to 11.25 degrees.
2. 6
×
REFCLK Multiplier engaged.
3. Powered-up mode selected.
4. Output = 10 MHz (for 180 MHz system clock).
In parallel mode, user would program the 40-bit control word
(composed of five 8-bit loads) as follows:
W0 = 00001001
W1 = 00001110
W2 = 00111000
W3 = 11100011
W4 = 10001110
If in serial mode, load the 40 bits starting from the LSB location
of W4 in the above “array,” loading from right to left, and end-
ing with the MSB of W0.
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相關代理商/技術參數 |
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|---|---|
| AD9851/CGPCB | 制造商:Analog Devices 功能描述:NCO/DDS, CMOS 180MHZ DDS/DAC SYNTHESIZER - Bulk 制造商:Rochester Electronics LLC 功能描述:DDS CLOCK DRIVER - Bulk |
| AD9851/FSPCB | 制造商:Analog Devices 功能描述:Evaluation Board For NCO/DDS, CMOS 180MHZ DDS/DAC Synthesizer 制造商:Analog Devices 功能描述:NCO/DDS, CMOS 180MHZ DDS/DAC SYNTHESIZER - Bulk |
| AD9851BRS | 功能描述:IC DDS DAC W/COMP 180MHZ 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9851BRSRL | 功能描述:IC DDS/DAC SYNTHESIZER 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9851BRSZ | 功能描述:IC SYNTHESIZER DDS/DAC 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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