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參數資料
| 型號： | AD9851 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 180 MHz DDS/DAC Synthesizer |
| 中文描述： | 180MHz的CMOS/DAC頻率合成器 |
| 文件頁數： | 13/23頁 |
| 文件大小： | 277K |
| 代理商： | AD9851 |
AD9851
–13–
REV. 0
PCB LAYOUT INFORMATION
The AD9851/CGPCB and AD9851/FSPCB evaluation boards
(Figures 22–25) represent typical implementations of the AD9851
and exemplify the use of high frequency/high resolution design
and layout practices. The printed circuit board that contains the
AD9851 should be a multilayer board that allows dedicated
power and ground planes. The power and ground planes should
(as much as possible) be free of etched traces that cause dis-
continuities in the planes. It is recommended that the top layer
of the board also contain an interspatial ground plane that makes
ground available without vias for the surface-mount devices. If
separate analog and digital system ground planes exist, they
should be connected together at the AD9851 evaluation board
for optimum performance.
Avoid running digital lines under the device as these will couple
unnecessary noise onto the die. The power supply lines to the
AD9851 should use as large a trace as possible to provide a low-
impedance path and reduce the effects of switching currents on
the power supply line. Fast switching signals like clocks should
use microstrip, controlled impedance techniques where possible.
Avoid crossover of digital and analog signal paths. Traces on
opposite sides of the board should run at right angles to each
other. This will reduce crosstalk between the lines.
Good power supply decoupling is also an important consider-
ation. The analog (AVDD) and digital (DVDD) supplies to the
AD9851 are independent and separately pinned-out to mini-
mize coupling between analog and digital sections of the device.
All analog and digital supply pins should be decoupled to AGND
and DGND respectively, with high quality ceramic chip capaci-
tors. To achieve best performance from the decoupling capaci-
tors, they should be placed as close as possible to the device. In
systems where a common supply is used to drive both the AVDD
and DVDD supplies of the AD9851, it is recommended that the
system’s AVDD supply be used.
Analog Devices applications engineering support is available to
answer additional questions on grounding and PCB layout. Call
1-800-ANALOGD.
EVALUATION BOARDS
Two versions of the AD9851 evaluation board are available.
The evaluation boards facilitate easy implementation of the
device for bench-top analysis and serve as a reference for PCB
layout.
The AD9851/FSPCB is intended for applications where the
device will primarily be used as a frequency synthesizer. This
version is optimized for connection of the AD9851 internal D/A
converter output to a 50
spectrum analyzer input. The inter-
nal comparator of the AD9851 is made available for use via wire
hole access. The comparator inputs are externally pulled to
opposing voltages to prevent comparator chatter due to floating
inputs. The DDS DAC output is unfiltered and no reference
oscillator is provided. This is done in recognition of the fact that
many users may find their presence to be a liability rather than
an asset. See Figure 22 for electrical schematic.
The AD9851/CGPCB is intended for applications using the
device as a CMOS output clock generator. It connects the
AD9851 DAC output to the internal comparator input via a
single-ended, 70 MHz low pass, 7th order, elliptic filter. To
minimize output jitter of the comparator, special attention has
been given to the low pass filter design. Primary considerations
were input and output impedances (200
) and a very steep
roll-off characteristic to attenuate unwanted, nearby alias sig-
nals. The high impedance of the filter allows the DAC to de-
velop 1 V p-p (with 10 mA) across the two 200
resistors at
the input and output of the filter. This voltage is entirely suffi-
cient to optimally drive the AD9851 comparator. This filter was
designed with the assumption that the AD9851 DDS is at full
clock speed (180 MHz). If this is not the case, filter specifica-
tions may need to change to achieve proper attenuation of
anticipated alias signals. BNC connectors allow convenient
observation of the comparator CMOS output and input, as well
as that of the DAC. No reference oscillator is provided for
reasons stated above. This model allows easy evaluation of the
AD9851 as a frequency and phase-agile CMOS output clock
source (see Figure 24 for electrical schematic).
Jitter Reduction Note
The AD9851/CGPCB has a wideband DDS fundamental out-
put, dc to 70 MHz, and the on-chip comparator has even more
bandwidth. To optimize low jitter performance users should
consider bandpass filtering of the DAC output if only a narrow
bandwidth is required. This will reduce jitter caused by spuri-
ous, nonharmonic signals above and below the desired signal.
Lowering the applied V
DD
helps in reducing comparator switch-
ing noise by reducing
V/
T of the comparator outputs. For
optimum jitter performance, users should avoid the very busy
digital environment of the on-chip comparator and opt for an
external, high speed comparator.
Both versions of the AD9851 evaluation boards are designed to
interface to the parallel printer port of a PC. The operating
software (C++) runs under Microsoft Windows
(3.1 and
Windows 95, NT is NOT supported) and provides a user-
friendly and intuitive format for controlling the functionality
and observing the performance of the device. The 3.5" disk
provided with the evaluation board contains an executable file
that displays the AD9851 function-selection screen. The
evaluation board may be operated with +3.0 V or +5 V sup-
plies. Evaluation boards are configured at the factory for an
external clock input. If the optional on-board crystal clock
source is installed, resistor R2 (50
) must be removed.
EVALUATION BOARD INSTRUCTIONS
Required Hardware/Software
Personal computer operating in Windows 3.1
or “95” environ-
ment (does not support Windows NT).
Printer port, 3.5" floppy drive, mouse and Centronics compat-
ible printer cable, +3 V to +5 V voltage supply.
Crystal clock oscillator or high frequency signal generator (sine
wave output) with dc offset capability.
AD9851 Evaluation Board Software disk and AD9851/FSPCB
or AD9851/CGPCB Evaluation Board
Setup
Copy the contents of the AD9851 disk onto the host PCs hard
drive (there are two files, WIN9851.EXE version 1.x and
Bwcc.dll). Connect the printer cable from computer to the
evaluation board. Use a good quality cable as some cables do
not connect every wire that the printer port supports.
Windows is a registered trademark of Microsoft Corportaion.
All other trademarks are the property of their respective holders.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9851/CGPCB | 制造商:Analog Devices 功能描述:NCO/DDS, CMOS 180MHZ DDS/DAC SYNTHESIZER - Bulk 制造商:Rochester Electronics LLC 功能描述:DDS CLOCK DRIVER - Bulk |
| AD9851/FSPCB | 制造商:Analog Devices 功能描述:Evaluation Board For NCO/DDS, CMOS 180MHZ DDS/DAC Synthesizer 制造商:Analog Devices 功能描述:NCO/DDS, CMOS 180MHZ DDS/DAC SYNTHESIZER - Bulk |
| AD9851BRS | 功能描述:IC DDS DAC W/COMP 180MHZ 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9851BRSRL | 功能描述:IC DDS/DAC SYNTHESIZER 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9851BRSZ | 功能描述:IC SYNTHESIZER DDS/DAC 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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