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參數資料
| 型號： | AD9851 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 180 MHz DDS/DAC Synthesizer |
| 中文描述： | 180MHz的CMOS/DAC頻率合成器 |
| 文件頁數： | 11/23頁 |
| 文件大小： | 277K |
| 代理商： | AD9851 |
AD9851
–11–
REV. 0
Results of Reset, Figure 14
– Phase Accumulator zeroed such that the output = 0 Hertz
(dc).
– Phase Offset register set to zero such that DAC IOUT = Full-
Scale output and IOUTB = zero mA output.
– Internal Programming Address pointer reset to W0.
– Power-down bit reset to “0” (power-down disabled).
– 40-bit Data Input Register is NOT cleared.
– 6
×
Reference Clock multiplier is disabled.
– Parallel programming mode selected by default.
XXXXX10X
FQ UD
W CLK
SYSCLK
DAC
STROBE
DATA (W0)
INTERNAL CLOCKS
DISABLED
Figure 15. Parallel-Load Power-Down Sequence/Internal
Operation
XXXXX00X
FQ UD
W CLK
DATA (W0)
INTERNAL CLOCKS
ENABLED
SYSCLK
Figure 16. Parallel-Load Power-Up Sequence (to Recover
from Power-Down)/Internal Operation
SYSCLK
RESET
A
OUT
t
RS
t
RH
t
RL
t
OL
COS (0
8
)
SYMBOL DEFINITION
t
RH
CLK DELAY AFTER RESET RISING EDGE
t
RL
RESET FALLING EDGE AFTER CLK
t
RR
RECOVERY FROM RESET 2 SYSCLK CYCLES
t
RS
MINIMUM RESET WIDTH
t
OL
RESET OUTPUT LATENCY
*
SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED
Figure 14. Master Reset Timing Sequence
MIN SPEC
3.5ns*
3.5ns*
5 SYSCLK CYCLES
13 SYSCLK CYCLES
t
RR
Entry to the serial mode, Figure 17, is via the parallel mode
which is selected by default after a RESET is asserted. One
needs only to program the first eight bits (word W0) with the
sequence xxxxx011as shown in Figure 17 to change from paral-
lel to serial mode. The W0 programming word may be sent over
the 8-bit data bus or hardwired as shown in Figure 18. After
serial mode is achieved, the user must follow the programming
sequence of Figure 19.
XXXXX011
FQ UD
W CLK
DATA (W0)
ENABLE
SERIAL MODE
Figure 17. Serial-Load Enable Sequence
Note: After serial mode is invoked, it is best to immediately
write a valid 40-bit serial word (see Figure 19), even if it is all
zeros, followed by a FQ_UD rising edge to flush the “residual”
data left in the DDS core. A valid 40-bit serial word is any word
where W33 is Logic 0.
28
27
26
25
1
2
3
4
AD9851
D3
D2
D1
D0
D4
D5
D6
D7
10k
V
+V
SUPPLY
Figure 18: Hardwired xxxxx011 Configuration for Serial-
Load Enable Word W0 in Figure 17
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9851/CGPCB | 制造商:Analog Devices 功能描述:NCO/DDS, CMOS 180MHZ DDS/DAC SYNTHESIZER - Bulk 制造商:Rochester Electronics LLC 功能描述:DDS CLOCK DRIVER - Bulk |
| AD9851/FSPCB | 制造商:Analog Devices 功能描述:Evaluation Board For NCO/DDS, CMOS 180MHZ DDS/DAC Synthesizer 制造商:Analog Devices 功能描述:NCO/DDS, CMOS 180MHZ DDS/DAC SYNTHESIZER - Bulk |
| AD9851BRS | 功能描述:IC DDS DAC W/COMP 180MHZ 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9851BRSRL | 功能描述:IC DDS/DAC SYNTHESIZER 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9851BRSZ | 功能描述:IC SYNTHESIZER DDS/DAC 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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