- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373969 > AD9858 (Analog Devices, Inc.) 1 GSPS Direct Digital Synthesizer PDF資料下載
參數(shù)資料
| 型號： | AD9858 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 1 GSPS Direct Digital Synthesizer |
| 中文描述： | 1 GSPS的直接數(shù)字頻率合成器 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大小： | 1412K |
| 代理商： | AD9858 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD9858
SYSCLK serves as the sample clock for the DAC and is fed to a
divide-by-8 frequency divider to produce SYNCLK. SYNCLK is
provided to the user on the SYNCLK pin. This enables
synchronization of external hardware with the AD9858’s
internal DDS clock. External hardware that is synchronized to
the SYNCLK signal can then be used to provide the frequency
update (FUD) signal to the AD9858. The FUD signal and
SYNCLK are used to transfer the internal buffer register
contents into the memory registers of the device. Figure 33
Rev. A | Page 20 of 32
shows a block diagram of the synchronization methodology,
and Figure 34 shows an I/O synchronization timing diagram.
Note that SYNCLK is also used to synchronize the assertion of
the profile select pins (PS0, PS1). The FUD, PS0, and PS1 pins
must be set up and held around the rising edge of SYNCLK.
These device inputs are designed for zero hold time and 3.5 ns
setup time.
U
REGISTER
MEMORY
EDGE
DETECTION
LOGIC
REFCLK
P0, P1
FUD
SYNCLK
0
2 GHz DIVIDER
DISABLE
SYNCLK
DISABLE
TO CORE LOGIC
BUFFER
MEMORY
÷ 2
1
0
1
0
D
Q
WR
ADDR
DATA
SYNCLK
D
Q
0
÷ 8
Figure 33. I/O Synchronization Block Diagram
SYNCLK
SYSCLK
FUD REGISTERED
FUD EDGE DETECTED
FUD REGISTERED
FUD EDGE DETECTED
VALUE 2
VALUE 1
IO BUFFER
MEMORY
CONTROL
REGISTER
DATA
VALUE 0
VALUE 1
VALUE 2
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
FUD
*
*
FUD IS AN INPUT PROVIDED BY THE USER THAT MUST BE SET UP AND HELD AROUND RISING EDGES OF SYNCLK. THE OCCURRENCE OF
THE RISING EDGE OF SYNCLK DURING THE HIGH STATE OF THE UPDATEREGS SIGNAL CAUSES THE BUFFER MEMORY CONTENTS TO BE
TRANSFERRED INTO THE CONTROL REGISTERS. SIMILARLY, A STATE CHANGE ON THE PS0 OR PS1 PINS IS EQUIVALENT TO ASSERTING A VALID
FUD SEQUENCE. NOTE: I/O UPDATES ARE SYNCHRONOUS TO THE SYNCLK SIGNAL, REGARDLESS OF THE SYNCHRONIZATION MODE SELECTED.
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
0
Figure 34. I/O Synchronization Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9858FDPCB | 1 GSPS Direct Digital Synthesizer |
| AD9859 | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSV | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSV-REEL7 | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9862PCB | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9858/FDPCB | 制造商:Analog Devices 功能描述:EVAL KIT FOR FRACTIONAL DIVIDER EVAL BD - Bulk |
| AD9858/PCBZ | 功能描述:BOARD EVAL FOR AD9858 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9858/TLPCB | 制造商:Analog Devices 功能描述:NCO/DDS, 1GSPS DIRECT DGTL SYNTHESIZER - Bulk |
| AD9858/TLPCBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| AD9858BSV | 制造商:Rochester Electronics LLC 功能描述:1000 MHZ DDS/DAC - Bulk 制造商:Analog Devices 功能描述:1GHZ DDS/DAC SMD 9858 TQFP100 制造商:Analog Devices 功能描述:Frequency Synthesizer,AD9858 1GHz TQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。