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參數資料
| 型號： | AD9864-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | 中頻數字化子系統 |
| 文件頁數： | 23/44頁 |
| 文件大小： | 1984K |
| 代理商： | AD9864-EB |
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AD9864
POWER CONTROL
To allow power consumption to be minimized, the AD9864
possesses numerous SPI programmable power-down and bias
control bits. The AD9864 powers up with all of its functional
blocks placed into a standby state, i.e., STBY register default is
0xFF. Each major block may then be powered up by writing a 0
to the appropriate bit of the STBY register. This scheme pro-
vides the greatest flexibility for configuring the IC to a specific
application as well as for tailoring the IC’s power-down and
wake-up characteristics. Table 11 summarizes the function of
each of the STBY bits. Note that when all the blocks are in
standby, the master reference circuit is also put into standby,
and thus the current is reduced further by 0.4 mA.
Table 11. Standby Control Bits
STBY Bit
Effect
7: REF
Voltage reference OFF;
all biasing shut down.
6: LO
LO synthesizer OFF,
IOUTL three-state.
5: CKO
Clock oscillator OFF.
4: CK
Clock synthesizer OFF,
IOUTC three-state. Clock
buffer OFF if ADC is OFF.
3: GC
Gain control DAC OFF.
GCP and GCN three-
state.
2: LNAMX
LNA and Mizer OFF.
CXVM, CXVL, and CXIF
three-state.
1: Unused
0: ADC
ADC OFF; Clock buffer
OFF if CLK synthesizer
OFF; VCM three-state;
clock to the digital filter
halted; digital outputs
static.
NOTES
1
When all blocks are in standby, the master reference circuit is also put into
standby, and thus the current is further reduced by 0.4 mA.
2
Wake-up time is dependent on programming and/or external components.
Rev. 0 | Page 23 of 44
Current
Reduction
(mA)
1
0.6
Wake-Up
Time (ms)
<0.1 (C
REF
= 4.7 nF)
Note 2
1.2
1.1
1.3
Note 2
Note 2
0.2
Depends
on C
GC
8.2
<2.2
9.2
<0.1
LO SYNTHESIZER
The LO synthesizer shown in Figure 38 is a fully programmable
phase-locked loop (PLL) capable of 6.25 kHz resolution at
input frequencies up to 300 MHz and reference clocks of up to
25 MHz. It consists of a low noise digital phase-frequency
detector (PFD), a variable output current charge pump (CP), a
14-bit reference divider, programmable A and B counters, and
a dual-modulus 8/9 prescaler.
The A (3-bit) and B (13-bit) counters, in conjunction with the
dual 8/9 modulus prescaler, implement an N divider with
N
= 8
×
B
+
A
. In addition, the 14-bit reference counter (R Counter)
allows selectable input reference frequencies, f
REF
,
at the PFD
input. A complete PLL can be implemented if the synthesizer is used
with an external loop filter and voltage controlled oscillator (VCO).
The A, B, and R counters can be programmed via the following
registers: LOA, LOB, and LOR. The charge pump output
current is programmable via the LOI register from 0.625 mA to
5.0 mA using the equation
(
)
mA
LOI
IPUMP
625
.
1
×
+
=
(2)
An on-chip fast acquire function (enabled by the LOF bit)
automatically increases the output current for faster settling
during channel changes. The synthesizer may also be disabled
using the LO standby bit located in the STBY register.
f
REF
f
REF
f
LO
f
LO
FROM
VCO
REF
BUFFER
÷
R
PHASE/
FREQUENCY
DETECTOR
FAST
ACQUIRE
CHARGE
PUMP
TO EXTERNAL
LOOP
FILTER
LO
BUFFER
÷
8/9
A. B
COUNTERS
LOR
LOA, LOB
0
Figure 38. LO Synthesizer
The LO (and CLK) synthesizer works in the following manner.
The externally supplied reference frequency,
f
REF
, is buffered
and divided by the value held in the R counter. The internal
f
REF
is then compared to a divided version of the VCO frequency,
f
LO
. The phase/frequency detector provides UP and DOWN
pulses whose widths vary, depending upon the difference in
phase and frequency of the detector’s input signals. The
UP/DOWN pulses control the charge pump, making current
available to charge the external low-pass loop filter when there
is a discrepancy between the inputs of the PFD. The output of
the low-pass filter feeds an external VCO whose output fre-
quency,
f
LO
, is driven such that its divided down version,
f
LO
,
matches that of
f
REF
,
thus closing the feedback loop.
The synthesized frequency is related to the reference frequency
and the LO register contents as follows:
(
)
REF
LO
f
LOR
LOA
LOB
f
×
+
×
=
/
8
(3)
Note that the minimum allowable value in the
LOB
register is 3
and its value must always be greater than that loaded into
LOA
.
An example may help illustrate how the values of
LOA
,
LOB
, and
LOR
can be selected. Consider an application employing a 13
MHz crystal oscillator, i.e.,
f
REF
= 13 MHz, with the requirement
that
f
REF
= 100 kHz and
f
LO
= 143 MHz, i.e., high side injection
with f
IF
= 140.75 MHz and
f
CLK
= 18 MSPS. LOR is selected to be
130 such that f
REF
= 100 kHz. The N-divider factor is 1430, which
can be realized by selecting
LOB
= 178 and
LOA
= 6.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9864-EBZ | 功能描述:BOARD EVAL FOR AD9864 制造商:analog devices inc. 系列:- 零件狀態:有效 類型:數字轉換器 頻率:10MHz ~ 300MHz 配套使用產品/相關產品:AD9864 所含物品:板 標準包裝:1 |
| AD9865 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9865BCP | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:10BIT MIXED SIGNAL CONVERTER 9865 |
| AD9865BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9865BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
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