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參數資料
| 型號： | AD9864-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | 中頻數字化子系統 |
| 文件頁數： | 29/44頁 |
| 文件大小： | 1984K |
| 代理商： | AD9864-EB |
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AD9864
constant over a ±3.5% range (i.e., ±35,000 ppm), suggesting
that most applications will not be required to retune over the
operating temperature range.
–15
12
11
N
10
LC ERROR (%)
9
8
0
10
–10
–5
15
BW = 75kHz
BW = 10kHz
BW = 30kHz
5
0
Figure 50. Typical Noise Figure Degradation from L and C
Component Drift (f
CLK
= 18 MSPS, f
IF
= 73.3501 MHz)
DECIMATION FILTER
The decimation filter shown in Figure 51 consists of an
f
CLK
/8
complex mixer and a cascade of three linear phase FIR filters:
DEC1, DEC2, and DEC3. DEC1 downsamples by a factor of 12
using a fourth order comb filter. DEC2 also uses a fourth order
comb filter, but its decimation factor is set by the M field of
Register 0x07. DEC3 is either a decimate-by-5 FIR filter or a
decimate-by-4 FIR filter, depending on the value of the K bit
within Register 0x07. Thus, the composite decimation factor
can be set to either 60 ×
M
or 48 ×
M
for
K
equal to 0 or 1,
respectively.
The output data rate (
f
OUT
) is equal to the modulator clock fre-
quency (
f
CLK
) divided by the digital filter’s decimation factor.
Due to the transition region associated with the decimation
filter’s frequency response, the decimation factor must be
selected such that
f
OUT
is equal to or greater than twice the sig-
nal bandwidth. This ensures low amplitude ripple in the pass
band along with the ability to provide further application-
specific digital filtering prior to demodulation.
4
OR
5
COS
SIN
DATA
FROM
Σ
-
MODULATOR
DEC1
SINC
4
FILTER
DEC2
SINC
4
FILTER
M + 1
DEC3
FIR
FILTER
COMPLEX
DATA TO
SSI PORT
Q
I
0
M
K
12
Figure 51.
Decimation Filter Architecture
Figure 52 shows the response of the decimation filter at a deci-
mation factor of 900 (
K
= 0,
M
= 14) and a sampling clock fre-
quency of 18 MHz. In this example, the output data rate (
f
OUT
)
is 20 kSPS, with a usable complex signal bandwidth of 10 kHz
centered around dc. As this figure shows, the first and second
alias bands (occurring at even integer multiples of
f
OUT
/2) have
the least attenuation but provide at least 88 dB of attenuation.
Note that signals falling around frequency offsets that are odd
integer multiples of
f
OUT
/2 (i.e., 10 kHz, 30 kHz, and 50 kHz)
will fall back into the transition band of the digital filter.
FREQUENCY (kHz)
–40
–100
0
30
10
20
–20
0
–60
–80
40
100
FOLD-
ING
POINT
±
5.0kHz PASS BAND
–120
70
80
60
50
90
–88dB
–88dB
–101dB
–103dB
d
0
Figure 52. Decimation Filter Frequency Response for
f
OUT
= 20 kSPS (f
CLK
= 18 MHz, OSR = 900)
Figure 53 shows the response of the decimation filter with a
decimation factor of 48 and a sampling clock rate of 26 MHz.
The alias attenuation is at least 94 dB and occurs for frequen-
cies at the edges of the fourth alias band. The difference
between the alias attenuation characteristics of Figure 52 and
those of Figure 53 is due to the fact that the third decimation
stage decimates by a factor of 5 for Figure 52 compared with a
factor of 4 for Figure 53.
0
–40
–100
–20
–60
–80
d
–120
FREQUENCY (MHz)
0
1.5
0.5
1.0
2.0
2.5
±
135.466kHz PASS BAND
–98dB
–115dB
–94dB
0
Figure 53. Decimation Filter Frequency Response for
f
OUT
= 541.666 kSPS (f
CLK
= 26 MHz, OSR = 48)
Figure 54 and Figure 55 show expanded views of the pass band
for the two possible configurations of the third decimation fil-
ter. When decimating by 60
n
(
K
= 0), the pass-band gain varia-
tion is 1.2 dB; when decimating by 48
n
(
K
= 1), the pass-band
gain variation is 0.9 dB. Normalization of full scale at band
center is accurate to within 0.14 dB across all decimation
modes. Figure 56 and Figure 57 show the folded frequency
response of the decimator for
K
= 0 and
K
= 1, respectively.
Rev. 0 | Page 29 of 44
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9864-EBZ | 功能描述:BOARD EVAL FOR AD9864 制造商:analog devices inc. 系列:- 零件狀態:有效 類型:數字轉換器 頻率:10MHz ~ 300MHz 配套使用產品/相關產品:AD9864 所含物品:板 標準包裝:1 |
| AD9865 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9865BCP | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:10BIT MIXED SIGNAL CONVERTER 9865 |
| AD9865BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9865BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
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