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參數資料
| 型號： | AD9866 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | 寬帶調制解調器混合信號前端 |
| 文件頁數： | 25/48頁 |
| 文件大小： | 1647K |
| 代理商： | AD9866 |
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AD9866
Rev. 0 | Page 25 of 48
0
RXCLK
RxSYNC
Rx[5:0]
Rx0LSB
Rx1MSB
Rx1LSB
Rx2MSB
Rx3LSB
Rx3MSB
t
DV
t
DH
Figure 54. Full-Duplex Rx Port Timing
To add flexibility to the full-duplex digital interface port,
several programming options are available in the SPI registers.
These options are listed in Table 14. The timing for the Tx[5:0]
and/or Rx[5:0] ports can be independently changed by selecting
either the rising or falling clock edge as the sampling/validating
edge of the clock. Inverting RXCLK (via Bit 1 or Reg. 0x0D)
affects both the Rx and Tx interface, because they both use
RXCLK.
Table 14. SPI Registers for Full-Duplex Interface
Address (Hex)
Bit
0x05
(2)
Description
OSCIN to RXCLK
0x0B
0x0C
0x0D
0x0E
(1)
(0)
(2)
(4)
(3)
(2)
(1)
(0)
(5)
(4)
(3)
(2)
(1)
(0)
(7)
Invert RXCLK
Disable RXCLK
Rx gain on Tx port
Invert TXSYNC
Tx 5/5 nibble
LS nibble first
TXCLK negative edge
Twos complement
Rx port three-state
Invert RXSYNC
Rx 5/5 nibble
LS nibble first
RXCLK negative edge
Twos complement
Low drive strength
The default Tx and Rx data input formats are twos complement,
but can be changed to straight binary. The default TXSYNC and
RXSYNC settings can be changed such that the first nibble of
the word appears while TXSYNC, RXSYNC, or both are high.
Also, the least significant nibble can be selected as the first
nibble of the word (LS nibble first). The output driver strength
can also be reduced for lower data rate applications.
Figure 55 shows a possible digital interface between an ASIC
and the AD9866. The AD9866 serves as the master generating
the required clocks for the ASIC. This interface requires that the
ASIC reserve 16 pins for the interface, assuming a 6-bit nibble
width and the use of the Tx port for RxPGA gain control. Note
that the ASIC pin allocation can be reduced by 3, if a 5-bit
nibble width is used and the gain (or gain strobe) of the RxPGA
is controlled via the SPI port.
0
TO
Tx DIGITAL
FILTER
10/12
AD9865/AD9866
FROM
Rx ADC
10/12
RXSYNC
TXSYNC
TX_SYNC
RXCLK
CLKOUT1
CLKOUT2
CLKIN
DIGITAL ASIC
OSCIN
FROM
CRYSTAL
OR MASTER CLK
GAIN
OPTIONAL
Tx Data[5:0]
Rx Data[5:0]
Rx[5:0]
RX_SYNC
M
D
Tx[5:0]
6
TO
Rx PGA
Figure 55. Example of a Full-Duplex Digital Interface
with Optional RxPGA Gain Control via Tx[5:0]
RxPGA CONTROL
The AD9866 contains a digital PGA in the Rx path that is used
to extend the dynamic range. The RxPGA can be programmed
over a 12 dB to +48 dB with 1 dB resolution using a 6-bit
word, and with a 0 dB setting corresponding to a 2 V p-p input
signal. The 6-bit word is fed into a LUT that is used to distribute
the desired gain over three amplification stages within the Rx
path. Upon power-up, the RxPGA gain register is set to its
minimum gain of 12 dB. The RxPGA gain mapping is shown
in Figure 56. Table 15 lists the SPI registers pertaining to the
RxPGA.
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| AD9866BCP | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:12BIT MIXED SIGNAL CONVERTER 9866 |
| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
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