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參數(shù)資料
型號(hào)： AD9866
廠商： Analog Devices, Inc.
英文描述： Broadband Modem Mixed Signal Front End
中文描述： 寬帶調(diào)制解調(diào)器混合信號(hào)前端
文件頁(yè)數(shù)： 27/48頁(yè)
文件大小： 1647K
代理商： AD9866
AD9866
TxPGA CONTROL
The AD9866 also contains a digital PGA in the Tx path distrib-
uted between the TxDAC and IAMP. The TxPGA is used to
control the peak current from the TxDAC and IAMP over a
7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. A
6-bit word is used to set the TxPGA attenuation according to
the mapping shown in Figure 58. The TxDAC gain mapping is
applicable only when Bit 0 of Reg. 0x0E is set, and only the
4 LSBs of the 6-bit gain word are relevant.
Rev. 0 | Page 27 of 48
0
6-BIT DIGITAL CODE (Decimal Equivalent)
T
0
8
16
24
32
40
48
56
64
0
–20
–16
–17
–18
–19
–14
–15
–12
–13
–10
–11
–8
–9
–6
–7
–2
–3
–4
–5
–1
TxDACs IOUTP OUTPUT
HAS 7.5dB RANGE
IAMPs IOUTN AND IOUTG
OUTPUTS HAS 19.5dB RANGE
Figure 58. Digital Gain Mapping of TxPGA
The TxPGA register can be updated via the PGA[5:0] port or
SPI port. The first method should be considered for fast updates
of the TxPGA register. Its operation is similar to the description
in the RxPGA Control section. The SPI port allows direct
update and readback of the TxPGA register via Reg. 0x0A with
an update rate limited to 1.6 MSPS (SCLK = 32 MHz). Bit 6 of
Reg 0x0A must be set for a read or write operation. Table 17
lists the SPI registers pertaining to the TxPGA. The TxPGA
control register default setting is for minimum attenuation
(0 dBFS) with the PGA[5:0] port disabled for Tx gain control.
Table 17. SPI Registers TxPGA Control
Address (Hex)
Bit
Description
0x0A
(6)
Enable TxPGA update via SPI
(5:0)
TxPGA gain code
0x0B
(6)
Select TxPGA via PGA[5:0]
(5)
Select RxPGA via PGA[5:0]
0x0E
(0)
TxDAC output (IAMP disabled)
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參數(shù)描述
AD9866BCP 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:12BIT MIXED SIGNAL CONVERTER 9866
AD9866BCPRL 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R
AD9866BCPZ 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤
AD9866BCPZRL 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤
AD9866CHIPS 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End
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