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| 型號(hào)： | AD9866 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號(hào)前端 |
| 文件頁(yè)數(shù)： | 4/48頁(yè) |
| 文件大小： | 1647K |
| 代理商： | AD9866 |
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AD9866
Parameter
3 dB Bandwidth
Stop Band Rejection (0.289 f
OSCIN
to 0.711 f
OSCIN
)
PLL CLK MULTIPLIER
OSCIN Frequency Range
Internal VCO Frequency Range
Duty Cycle
OSCIN Impedance
CLKOUT1 Jitter
5
CLKOUT2 Jitter
6
CLKOUT1 and CLKOUT2 Duty Cycle
7
Rev. 0 | Page 4 of 48
Temp
Full
Full
Full
Full
Full
25°C
25°C
25°C
Full
Test Level
V
V
IV
IV
II
V
III
III
III
Min
5
20
40
45
Typ
Max
80
200
60
55
Unit
f
OUT
/f
DAC
dB
MHz
MHz
%
Μ//pF
ps rms
ps rms
%
0.1202
50
100//3
12
6
1
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).
2
TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 , F
OUT
= 5 MHz, 4× interpolation.
3
IOUN full-scale current = 80 mA, f
OSCIN
= 80 MHz, f
DAC
=160 MHz, 2× interpolation.
4
Use external amplifier to drive additional load.
5
Internal VCO operates at 200 MHz , set to divide-by
-
1.
6
Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN.
7
CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.
RX PATH SPECIFICATIONS
Table 2. AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; half- or full-duplex operation with CONFIG = 0 default
power bias settings, unless otherwise noted
Parameter
Rx INPUT CHARACTERISTICS
Input Voltage Span (RxPGA gain = 10 dB)
Input Voltage Span (RxPGA gain = +48 dB)
Input Common-Mode Voltage
Differential Input Impedance
Temp
Full
Full
25°C
25°C
Test Level
III
III
III
III
Min
Typ
6.33
8
1.3
400
4.0
53
2.7
2.4
12
48
1
Monotonic
0.5
20
±1
20
100
12
10.5
10.0
Max
Unit
V p-p
mV p-p
V
pF
MHz
nV/rtHz
nV/rtHz
dB
dB
dB
dB
dB
MHz
dB
dB
ns
ns
Bits
MSPS
Cycles
Cycles
Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB)
Input Voltage Noise Density (RxPGA Gain = 36 dB, f
3 dBF
= 26 MHz)
Input Voltage Noise Density (RxPGA Gain = 48 dB, f
3 dBF
= 26 MHz)
RxPGA CHARACTERISTICS
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
Gain Range Error
RxLPF CHARACTERISTICS
Cutoff Frequency (f
3 dBF
) range
Attenuation at 55.2 MHz with f
3 dBF
= 21 MHz
Pass-Band Ripple
Settling Time to 5 dB RxPGA Gain Step @ f
ADC
= 50 MSPS
Settling Time to 60 dB RxPGA Gain Step @ f
ADC
= 50 MSPS
ADC DC CHARACTERISTICS
Resolution
Conversion Rate
RX PATH LATENCY
1
Full-Duplex Interface
Half-Duplex Interface
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
NA
FULL
Full
Full
III
III
III
III
III
III
III
III
III
III
III
III
III
NA
II
V
V
15
5
35
80
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9866BCP | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:12BIT MIXED SIGNAL CONVERTER 9866 |
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| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤(pán)（7x7） 包裝:托盤(pán) |
| AD9866BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤(pán)（7x7） 包裝:托盤(pán) |
| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
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