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參數資料
| 型號： | AD9875 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調制解調器混合信號前端 |
| 文件頁數： | 16/24頁 |
| 文件大小： | 288K |
| 代理商： | AD9875 |
REV. 0
AD9875
–16–
D/A CONVE RT E R
T he AD9875 DAC provides differential output current on the
T x+ and T x– pins. T he value of the output currents are compli-
mentary, meaning that they will always sum to I
FS
, the full-scale
current of the DAC. For example, when the current from T x+ is
at full-scale, the current from T x– is zero. T he two currents will
typically drive a resistive load which will convert the output
currents to a voltage. T he T x+ and T x– output currents are
inherently ground seeking and should each be connected to
matching resistors, R
L
, that are tied directly to AGND.
T he full-scale output current of the DAC is set by the value of
the resistor placed from the FSADJ pin to AGND. T he relation-
ship between the resistor,
R
SET
, and the full-scale output current
is governed by the following equation:
I
FS
= 39.4/
R
SET
T he full-scale current can be set from 2 mA to 20 mA. Gener-
ally, there is a trade-off between DAC performance and power
consumption. T he best DAC performance will be realized at an
I
FS
of 20 mA. However, the value of I
FS
adds directly to the
overall current consumption of the device.
T he single-ended voltage output appearing at the
Tx+
and
Tx–
nodes are:
V
Tx+
=
I
Tx+
×
R
L
V
Tx–
=
I
Tx–
×
R
L
Note that the full-scale voltage of
V
Tx+
and
V
Tx–
should not
exceed the maximum output compliance range of 1.5 V to pre-
vent signal compression. T o maintain optimum distortion and
linearity performance, the maximum voltages at
V
Tx+
and
V
Tx–
should not exceed 0.5 V.
T he single ended full-scale voltage at either output node will be:
V
FS
=
I
FS
×
R
L
T he differential voltage, V
DIFF
, appearing across V
T x+
and V
T x–
is:
V
DIFF
=
(I
Tx+
– I
Tx–
)
×
R
L
and
V
DIFF_FS
=
I
FS
×
R
L
For optimum performance, a differential output interface is
recommended since any common-mode noise or distortion can
be supressed.
It should be noted that the differential output impedance of the
DAC is 2
×
R
L
and any load connected across the two output
resistors will load down the output voltage accordingly.
RE CE IVE PAT H DE SCRIPT ION
T he receive path consists of a two-stage PGA, a continuous time,
4-pole LPF, an ADC, a digital HPF and a digital data multiplexer.
Also working in conjunction with the receive path is an offset
correction circuit and a digital phase lock loop. Each of these
blocks will be discussed in detail in the following sections.
PROGRAMMABLE GAIN AMPLIFIE R
T he PGA has a programmable gain range from –6 dB to +36 dB
if the narrower (approximately 12 MHz) LPF bandwidth is
selected, or if the LPF is bypassed. If the wider (approximately
26 MHz) LPF bandwidth is selected, the gain range is –6 dB to
+30 dB. T he PGA is comprised of two sections, a Continuous
T ime PGA (CPGA) and a Switched Capacitor PGA (SPGA).
T he CPGA has possible gain settings of –6, 0, 6, 12, 18, and 24.
The SPGA has possible gain settings of 0, 2, 4, 6, 8, 10, and 12 dB.
T able I shows how the gain is distributed for each programmed
gain setting.
T he CPGA input appears at the device Rx+ and Rx– input pins.
T he input impedance of this stage is nominally 270
differen-
tial and is not gain dependent. It is best to ac-couple the input
signal to this stage and let the inputs self bias. T his will lower the
offset voltage of the input signal, which is important at higher
gains, as any offset will lower the output compliance range of the
CPGA output. When the inputs are driven by direct coupling, the
dc level should be AVDD/2. However, this could lead to larger dc
offsets and consequently reduce the dynamic range of the Rx path.
LOW-PASS FILT E R
T he Low-Pass Filter (LPF) is a programmable, multistage,
fourth order low-pass filter comprised of two real poles and a
complex pole pair. T he first real pole is implemented within the
CPGA. T he second filter stage implements a complex pair of
poles. T he last real pole is implemented in a buffer stage that
drives the SPGA.
T here are two passband settings for the LPF. Within each pass-
band the filters are tunable over about a 30% frequency range.
T he formula for the cutoff frequency is:
f
CUTOFF LOW
=
f
ADC
×
64
/(
64
+ Target)
f
CUTOFF HIGH
=
f
ADC
×
158
/(
64
+ Target)
Where
Target
is the decimal value programmed as the tuning
target in Register 5.
T his filter may also be bypassed by setting Bit 0 of Register 4.
In this case, the bandwidth of the Rx path will decrease with
increasing gain and be approximately 50 MHz at the highest
gain settings.
ADC
T he AD9875’s analog-to-digital converter implements a pipelined
multistage architecture to achieve high sample rates while con-
suming low power. T he ADC distributes the conversion over
several smaller A/D subblocks, refining the conversion with
progressively higher accuracy as it passes the results from stage
to stage. As a consequence of the distributed conversion, ADCs
require a small fraction of the 2
N
comparators used in a tradi-
tional n-bit flash-type A/D. A sample-and-hold function within
each of the stages permits the first stage to operate on a new
input sample while the remaining stages operate on preceding
samples. Each stage of the pipeline, excluding the last, consists
of a low resolution flash A/D connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). T he residue
amplifier amplifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipe-
line. One bit of redundancy is used in each one of the stages to
facilitate digital correction of flash errors. T he last stage simply
consists of a flash A/D.
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