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參數資料
| 型號： | AD9875 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調制解調器混合信號前端 |
| 文件頁數： | 21/24頁 |
| 文件大小： | 288K |
| 代理商： | AD9875 |
REV. 0
AD9875
–21–
RE GIST E R PROGRAMMING DE FINIT IONS
RE GIST E R 0—RE SE T /SPI Configuration
Bit 5: Software Reset
Setting this bit high resets the chip. T he PLLs will relock to the
input clock and all registers (except Register 0
×
0, Bit 6) revert
to their default values. Upon completion of the reset, Bit 5 is
reset to 0.
T he content of the interpolator stages are not cleared by software
or hardware resets. It is recommended to “flush” the transmit
path with zeros before transmitting data.
Bit 6: LSB/MSB First
Setting this bit high causes the serial port to send and receive
data least significant bit (LSB) first. T he default low state con-
figures the serial port to send and receive data most significant
bit (MSB) first.
RE GIST E RS 1 and 2—Power-Down
T he combination of the PWR DN pin and Registers 1 and 2
allow for the configuration of two separate pin selectable power
settings. T he PWR DN pin selects between two sets of individu-
ally programmed operation modes.
When the PWR DN pin is low, the functional blocks corre-
sponding to the bits set in register 1 will be powered down.
When the PWR DN pin is high, the functional blocks corre-
sponding to the bits set in Register 2 will be powered down
Bit 0: Power-Down Receive Filter and CPGA
Setting this bit high powers down and bypasses the Rx LPF and
coarse programmable gain amplifier.
Bit 1: Power-Down ADC and FPGA
Setting this bit high powers down the ADC and fine program-
mable gain amplifier (FPGA).
Bit 2: Power-Down Rx Reference
Setting this bit high powers down the ADC reference. T his bit
should be set if an external reference is applied.
Bit 3: Power-Down Interpolators
Setting this bit high powers down the transmit digital interpola-
tors. It does not clear the content of the data path.
Bit 4: Power-Down DAC
Setting this bit high powers down the transmit DAC.
Bit 5, Bit 6: Power-Down PLL-A, PLL-B
Setting these bits high powers down the on-chip phase lock
loops which generated CLK -A and CLK -B respectively. When
powered down these clocks are high impedance.
Bit 7: Power-Down Regulator
Setting this bit high powers down the on-chip voltage control regulator.
RE GIST E R 3—CLOCK SOURCE CONFIGURAT ION
T he AD9875 integrates two independently programmable PLLs
referred to as PLL-A and PLL-B. T he output of the PLLs are
used to generate all the chips internal and external clock signals
from the f
CLK IN
signal. All T x path clock signals are derived
from PLL-A. If f
CLK IN
is programmed as the ADC sampling
clock source, the Rx port clocks are also derived from PLL-A.
Otherwise, the ADC sampling clock is PLL-B/2 and the Rx path
clocks are derived from PLL-B.
Bit 1,0: PLL-A Multiplier
Bits 1 and 0 determine the multiplication factor (L) for PLL-A
and the DAC sampling clock frequency,
f
DAC
.
f
DAC
=
L
×
f
CLKIN
Bit 1,0
0,0: L = 1
0,1: L = 2
1,0: L = 4
1,1: L = 8
Bit 5 to 2: PLL-B Multiplier/Divider
Bits 5 to 2 determine the multiplication factor (M) and division
factor (N) for PLL-B and the CLK -B frequency. For multiplexed
10-/12-bit data, f
CLK -B
= f
CLK IN
×
M/N. For nonmultiplexed 6-bit
data, f
CLK -B
= (f
CLK IN
/2)
×
M/N. All nine combinations of M and N
values are valid, yielding seven unique M/N ratios.
Bit 5,4
0,0: M = 3
0,1: M = 4
1,0: M = 6
Bit 3,2
0,0: N = 2
0,1: N = 4
1,0: N = 1
Bit 6: ADC Clock Source PLL-B/2
Setting Bit 6 high selects PLL-B/2 as the ADC sampling Clock
source. In this mode, the Rx data and CLK -B will run at a rate
of f
CLK -B
. RxSYNC will run at f
CLK -B
/2.
Setting Bit 6 low selects the f
CLK IN
signal as the ADC sampling
clock source. T his mode of operation yields the best ADC
performance if an external crystal is used or a low jitter clock
source drives the OSCIN pin.
Bit 7: T x Port Negative E dge Sampling
Setting Bit 7 high will cause the T x port to sample the T xDAT A
and T xSYNC on the falling edge of CLK -A. By default, the T x
Port sampling occurs on the rising edge of CLK -A. T he timing
is shown in Figure 5.
RE GIST E R 4—RE CE IVE FILT E R SE LE CT ION
T he AD9875 receive path has a continuous time 4-pole LPF
and a 1-pole digital HPF. T he 4-pole LPF has two selectable
cutoff frequencies. Additionally, the filter can be tuned around
those two cutoff frequencies. T hese filters can also be bypassed
to different degrees as described below.
T he continuous time 4-pole low-pass filter is automatically
calibrated to one of two selectable cutoff frequencies.
T he cutoff frequency f
CUT OFF
is described as a function of the
ADC sampling frequency f
ADC
and can be influenced (
±
30%) by
the Rx-Filter T uning T arget word in Register 5.
f
CUTOFF LOW
=
f
ADC
×
64/(
Target +
64)
f
CUTOFF HIGH
=
f
ADC
×
158/(
Target +
64)
Bit 0: Rx LPF Bypass
Setting this bit high bypasses the 4-pole L PF . T he filter is
automatically powered down when this bit is set.
Bit 1: E nable 1-Pole Rx LPF
The AD9875 can be configured with an additional 1-pole ~16 MHz
input filter for applications that require steeper filter roll-off or
want to use the 1-pole filter instead of the 4-pole receive
L ow-Pass filter. T he 1-pole filter is untrimmed and subject to
cutoff frequency variations of
±
20%.
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