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參數資料
| 型號： | AD9875 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調制解調器混合信號前端 |
| 文件頁數： | 17/24頁 |
| 文件大小： | 288K |
| 代理商： | AD9875 |
REV. 0
AD9875
–17–
AINP
AINN
GAIN
SHA
GAIN
CORRECTION LOGIC
A/D
D/A
SHA
A/D
D/A
A/D
AD9875
Figure 2. ADC Theory of Operation
T he digital data outputs of the ADC are represented in two’s
complement format. T hey saturate to full-scale or zero when the
input signal exceeds the input voltage range.
T he two’s complement data format is shown below:
011 . . 11: Maximum
000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB
111 . . 10: Midscale – 2 LSB
100 . . 00: Minimum
T he Maximum value will be output from the ADC when the
Rx+ input is 1V or more greater than the Rx– input. T he Mini-
mum value will be output from the ADC when the Rx– input is
1 V or more greater than the Rx+ input. T his results in a full-scale
ADC voltage of 2 Vppd.
T he data can be translated to straight binary data format by
simply inverting the most significant bit.
T he best ADC performance will be achieved when the ADC
clock source is selected from f
OSCIN
and f
OSCIN
is provided from
a low jitter clock source. T he amount of degradation from jitter
on the ADC clock will depend on how quickly the input is varying
at the sampling instance. T PC 36 charts this effect in the form
of ENOB vs. input frequency for the two clocking scenarios.
T he maximum sample rate of the ADC in full-precision mode,
that is outputting 10 bits, is 55 MSPS. T PC 33 shows the ADC
performance in ENOB vs. f
ADCCLK
. T he maximum sample rate
of the ADC in half-precision mode, that is outputting five bits,
is 64 MSPS. T he timing of the interface is fully described in the
Receive T iming section of this data sheet.
DIGIT AL HPF
Following the ADC there is a bypassable digital HPF. T he
response is a single pole IIR HPF. T he transfer function is
approximately:
H(z)
=
(Z –
0.99994
)/(Z –
0.98466
)
Where the sampling period is equal to the ADC clock period.
T his results in a 3 dB frequency approximately 1/400th of the
ADC sampling rate. T he transfer functions are plotted for
32 MSPS and 50 MSPS in T PC 31 and T PC 32.
T he digital HPF introduces a 1 ADC clock cycle latency. If the
HPF function is not desired, the HPF can be bypassed and the
latency will not be incurred.
CLOCK AND OSCILLAT OR CIRCUIT RY
T he AD9875’s internal oscillator generates all sampling clocks
from a fundamental frequency quartz crystal. Figure 3a shows
how the quartz crystal is connected between OSCIN (Pin 1) and
X T AL (Pin 48) with parallel resonant load capacitors as specified
by the crystal manufacturer. T he internal oscillator circuitry can
also be overdriven by a T T L level clock applied to OSCIN with
X T AL left unconnected.
T he PLL has a frequency capture range between 10 MHz and 64 MHz.
VOLT AGE RE GULAT OR CONT ROLLE R
T he AD9875 contains an on-chip voltage regulator controller
(VRC) for providing a linear 1.3 V supply for low voltage digital
circuitry or other external use. T he VRC consists of an op amp
and a resistive voltage divider. As shown in Figure 3b, the resis-
tive divider establishes a voltage of 1.3 V at the inverting input
of the amplifier when DVDD is equal to its nominal voltage of
3.3 V. T he feedback loop around the op amp will adjust the gate
voltage such that the voltage at the FB pin, V
FB
, will be equal to
the voltage at the inverting input of the op amp.
XTAL
C2
AD9875
OSCIN
C1
XTAL
Y1
Figure 3a. Connections for Fundamental Mode Crystal
DVDD
GATE
FB
V
FB
= 1.3V
V
OUT
SI2301
1.3R
2R
3.3V
S
G
D
C
AD9875
Figure 3b. Connections for a 1.3 V Linear Regulator
T he maximum current output from the circuit is largely depen-
dent on the MOSFET device. For the SI2301 shown, 250 mA
can be delivered. T he regulated output voltage should have bulk
decoupling and high frequency decoupling capacitors to ground
as required by the load. T he regulator circuit will be stable for
capacitive loads between 0.1
μ
F and 47
μ
F.
It should be noted that the regulated output voltage, V
FB
, is
proportional to DVDD. T herefore, the percentage variation in
DVDD will also be seen at the regulated output voltage. T he
load regulation is roughly equal to the on resistance of the
MOSFET device chosen. For the SI2301, this is about 60 m
.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9875BST | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10B BROADBAND MODEM MXFE CONVERTER - Tape and Reel |
| AD9875BSTRL | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP T/R |
| AD9875BSTZ | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP |
| AD9875-EB | 制造商:Analog Devices 功能描述: |
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