
REV. 0
–2–
AD9875–SPECIFICATIONS
T est
Level
Parameter
T emp
Min
T yp
Max
Unit
OSC IN CHARACT ERIST ICS
Frequency Range
Duty Cycle
Input Capacitance
Input Impedance
Full
25
°
C
25
°
C
25
°
C
II
II
III
III
10
40
64
60
MHz
%
pF
M
50
3
100
CLOCK OUT PUT CHARACT ERIST ICS
CLK A Jitter (f
CLK A
Derived from PLL)
CLK A Duty Cycle
CLK B Jitter (f
CLK B
Derived from PLL)
CLK B Duty Cycle
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
14
50
±
5
33
50
±
5
ps rms
%
ps rms
%
T x CHARACT ERIST ICS
T x Path Latency, 4
×
Interpolation
Interpolation Filter Bandwidth (–0.1 dB)
4
×
Interpolation, LPF
2
×
Interpolation, LPF
T xDAC
Resolution
Conversion Rate
Full-Scale Output Current
Voltage Compliance Range
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Phase Noise @ 1 kHz Offset, 10 MHz Signal
Signal-to-Noise and Distortion (SINAD)
10 MHz Analog Out AD9875 (20 MHz BW)
Wideband SFDR (to Nyquist, 64 MHz Max)
5 MHz Analog Out
10 MHz Analog Out
Narrowband SFDR (3 MHz Window):
10 MHz Analog Out
IMD (f1 = 6.9 MHz, f2 = 7.1 MHz)
Full
II
82
f
DAC
Cycles
Full
Full
II
II
13
26
MHz
MHz
Full
Full
Full
Full
Full
Full
25
°
C
25
°
C
25
°
C
25
°
C
II
II
II
II
II
II
III
III
III
III
10
Bits
MHz
mA
V
% FS
μ
A
LSB
LSB
pF
dBc/Hz
10
2
–0.5
–5
0
128
20
+1.5
+5
19
10
±
2
7
0.5
1
5
–90
Full
25
°
C
25
°
C
25
°
C
I
III
III
III
59
61
dB
78
72
dBc
dBc
25
°
C
25
°
C
III
III
80
–76
dBc
dBFS
Rx PAT H CHARACT ERIST ICS
Resolution
Conversion Rate
Pipeline Delay, ADC Clock Cycles
DC Accuracy
Differential Nonlinearity
Integral Nonlinearity
Dynamic Performance
(A
IN
= –0.5 dBFS, f = 5 MHz)
@ f
OSCIN
= 32 MHz
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
T otal Harmonic Distortion (T HD)
Spurious Free Dynamic Range (SFDR)
Dynamic Performance
(
A
IN
= –0.5 dBFS, f = 10 MHz
)
@ F
PLLB/2
= 50 MHz
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
T otal Harmonic Distortion (T HD)
Spurious Free Dynamic Range (SFDR)
Full
Full
Full
II
II
II
10
Bits
MHz
Cycles
7.5
55
5.5
25
°
C
25
°
C
II
II
–1.0
–2.0
±
0.25
±
0.5
+1.0
+2.0
LSB
LSB
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
III
59.6
9.5
60
–65
68
dB
Bits
dB
dB
dB
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
III
54
8.6
55
–61
68
dB
Bits
dB
dB
dB
(V
S
= 3.3 V 10%, f
OSCIN
= 32 MHz, f
DAC
= 128 MHz, Gain = –6 dB, R
SET
= 4.02 k ,
100 DAC single-ended load, unless otherwse noted. )