- 您現在的位置：買賣IC網 > PDF目錄373970 > AD9882 (Analog Devices, Inc.) Dual Interface for Flat Panel Displays PDF資料下載
參數資料
| 型號： | AD9882 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | 雙接口的平板顯示器 |
| 文件頁數： | 10/36頁 |
| 文件大小： | 370K |
| 代理商： | AD9882 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
REV. A
–10–
AD9882
PIN FUNCTION DETAIL (ANALOG INTERFACE)
INPUTS
R
AIN
Analog Input for RED Channel
G
AIN
Analog Input for GREEN Channel
B
AIN
Analog Input for BLUE Channel
High impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. For RGB, the three channels are
identical and can be used for any colors, but
colors are assigned for convenient reference.
For proper 4:2:2 formatting in a YPbPr application,
the Y must be connected to the G
AIN
input, the
Pb must be connected to the B
AIN
input, and the
Pr must be connected to the R
AIN
input.
They accommodate input signals ranging from
0.5 V to 1.0 V full scale. Signals should be
ac-coupled to these pins to support clamp
operation.
HSYNC
Horizontal Sync Input
This input receives a logic signal that establishes
the horizontal timing reference and provides the
frequency reference for pixel clock generation.
The logic sense of this pin is controlled by Serial
Register Bit 10H, Bit 6 (Hsync Polarity). Only
the leading edge of Hsync is active; the trailing
edge is ignored. When Hsync Polarity = 0, the
falling edge of Hsync is used. When Hsync
Polarity = 1, the rising edge is active.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold of
1.5 V.
Electrostatic Discharge (ESD) protection diodes
will conduct heavily if this pin is driven more
than 0.5 V above the maximum tolerance voltage
(3.3 V), or more than 0.5 V below ground.
VSYNC
Vertical Sync Input
This is the input for vertical sync.
SOGIN
Sync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high speed comparator with an internally gener-
ated threshold, which is set by the value of
register 0FH, Bits 7
–
3.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.
When not used, this input should be left uncon-
nected. For more details on this function and
how it should be configured, refer to the Sync-
on-Green section.
SOGOUT
Sync-on-Green Slicer Output
This pin can be programmed to produce either
the output from the Sync-on-Green slicer com-
parator or an unprocessed but delayed version of
the Hsync input. See the Sync Processing Block
Diagram, Figure 18, to view how this pin is
connected.
Note: The output from this pin is the composite
SYNC without additional processing from the
AD9882.
External Filter Connection
For proper operation, the pixel clock generator
PLL requires an external filter. Connect the
filter shown in Figure 6 to this pin. For optimal
performance, minimize noise and parasitics on
this node.
REFBYPASS Internal Reference BYPASS
Bypass for the internal 1.25 V band gap refer-
ence. It should be connected to ground through
a 0.1
m
F capacitor.
The absolute accuracy of this reference is
±
4%,
and the temperature coefficient is
±
50 ppm,
which is adequate for most AD9882 applica-
tions. If higher accuracy is required, an external
reference may be employed instead.
MIDBYPASS Midscale Voltage Reference BYPASS
Bypass for the internal midscale voltage refer-
ence. It should be connected to ground through
a 0.1
m
F capacitor. The exact voltage varies with
the gain setting of the RED channel.
HSOUT
Horizontal Sync Output
A reconstructed and phase-aligned version of
the Hsync input. The duration of Hsync can
only be programmed on the analog interface,
not the digital.
DATACK
Data Output Clock
The data clock output signal is used to clock the
output data and HSOUT into external logic.
It is produced by the internal clock generator
and is synchronous with the internal pixel
sampling clock.
When the sampling time is changed by adjusting
the PHASE register, the output timing is shifted
as well. The Data, DATACK, and HSOUT
outputs are all moved so the timing relationship
among the signals is maintained.
VSOUT
Vertical Sync Output
The separated Vsync from a composite signal or
a direct pass-through of the Vsync input. The
polarity of this output can be controlled via
Register 10H, Bit 2. The placement and duration
in all modes is set by the graphics transmitter.
FILT
相關PDF資料 |
PDF描述 |
|---|---|
| AD9883ABST-RL140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKST-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKST-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883A | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883ABST-RL110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9882/PCB | 制造商:Analog Devices 功能描述:DUAL INTRFC FOR FLAT PNL DISPLAY 100LQFP - Bulk |
| AD9882A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882AKSTZ-100 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9882AKSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
發布緊急采購，3分鐘左右您將得到回復。