
REV. A
AD9882
–29–
14
A bit that can put the outputs in a high impedance mode. This
applies to the 24 data output pins, HSOUT, VSOUT, and DE Pins.
3
PDO
Power-Down Outputs
Table XXXII. Power-Down Output Settings
PDO
Function
0
1
Normal operation
Three-state
The default for this register is 0. (This option works on both the analog and
digital interfaces.)
14
This bit is used to set the HDCP Slave Port address.
2
HDCP Address
Table XXXIII. HDCP Address Settings
Address Bit
Result
0
1
0 for HDCP Slave Port
1 for HDCP Slave Port
The default for this register is 0.
14
This bit is used to control chip power-down. See the section on
power management for details about which blocks are actually
powered down.
1
PWRDN
Table XXXIV. Power-Down Settings
Select
Result
0
1
Power-down
Normal operation
The default for this register is 1.
14
A bit that configures the output data in 4:2:2 mode. This mode
can be used to reduce the number of data lines used from 24
to 16 for applications using YPbPr graphics signals. A timing
diagram for this mode is shown in Figure 9. Recommended
input and output configurations are shown in Table XXXVI.
In 4:2:2 mode, the RED and BLUE channels can be interchanged
to help satisfy board layout or timing requirements, but the
GREEN channel must be configured for Y.
0
4:2:2 Output Mode Select
Table XXXV. 4:2:2 Output Mode Select
Select
Output Mode
0
1
4:4:4
4:2:2
Table XXXVI. 4:2:2 Input/Output Configuration
Channel
Input Connection
Output Format
RED
GREEN
BLUE
Pr
Y
Pr
Pb/Pr
Y
High impedance
15
This bit is used to indicate when activity is detected on the
Hsync input pin (Pin 79). If Hsync is held high or low, activity
will not be detected.
7
Hsync Detect
Table XXXVII. Hsync Detection Results
Detect
Function
0
1
No activity detected
Activity detected
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
15
This bit is used to indicate when sync activity is detected on the
Sync-on-Green input pin (Pin 64).
6
Sync-on-Green Detect
Table XXXVIII. Sync-on-Green Detection Results
Detect
Function
0
1
No activity detected
Activity detected
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
Note: If no Sync signal is presented on the GREEN video input,
normal video may still trigger activity.
15
This bit is used to indicate when activity is detected on the
Vsync input pin (Pin 80). If Vsync is held high or low, activity
will not be detected.
5
Vsync Detect
Table XXXIX. Vsync Detection Results
Detect
Function
0
1
No activity detected
Activity detected
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
15
This bit is used to indicate when activity is detected on the
digital interface clock input.
4
Digital Interface Clock Detect
Table XL. Digital Interface Clock Detection Results
Detect
Function
0
1
No activity detected
Activity detected
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.