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參數資料
| 型號： | AD9882 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | 雙接口的平板顯示器 |
| 文件頁數： | 28/36頁 |
| 文件大小： | 370K |
| 代理商： | AD9882 |
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REV. A
–28–
AD9882
11
A bit that determines whether the GREEN channel is clamped
to ground or to midscale.
5
GREEN Clamp Select
Table XXIV. GREEN Clamp Select Settings
Clamp
Function
0
1
Clamp to ground
Clamp to midscale (Pin 74)
The default setting for this register is 0.
11
A bit that determines whether the BLUE channel is clamped to
ground or to midscale.
4
BLUE Clamp Select
Table XXV. BLUE Clamp Select Settings
Clamp
Function
0
1
Clamp to ground
Clamp to midscale (Pin 74)
The default setting for this register is 0.
11
This bit is used to enable or disable the coast signal. If coast is
enabled, the additional decision of using the Vsync input pin or
the output from the sync separator needs to be made (Register
10H, Bits 1, 0). To disable coast, the user must set Register 11H,
Bit 2 to 1 and 11H, Bit 1 to 1.
3
Coast Select
Table XXVI. Coast Enable Settings
Select
Result
0
1
Coast disabled
Internally generated coast signal
The default for this register is 1.
11
This register is used to override the internal circuitry that deter-
mines the polarity of the coast signal going into the PLL. When
disabling coast, Register 11, Bit 2 must be set to 1 and Register
11H, Bit 1 must be set to 1. This register only works when Coast
is disabled. It does not work with internal Coast.
2
Coast Input Polarity Override
Table XXVII. Coast Input Polarity Override Settings
Override Bit
Result
0
1
Coast polarity determined by chip
Coast polarity determined by user
The default for coast polarity override is 0.
11
A bit to indicate the polarity of the coast signal that is applied to
the PLL coast input.
This register can only be used when coast is disabled and
Register 11H, Bit 2 is set to 1.
1
Coast Input Polarity
Table XXVIII. Coast Input Polarity Settings
CSTPOL
Function
0
1
Active LOW
Active HIGH
The power-up default value is CSTPOL = 1.
12
This register allows the coast signal to be applied prior to the
Vsync signal. This is necessary in cases where pre-equalization
pulses are present. This register defines the number of edges
that will be filtered before Vsync on a composite sync.
The default is 0.
13
7–0
Post-Coast
This register allows the coast signal to be applied following the
Vsync signal. This is necessary in cases where post-equalization
pulses are present. The step size for this control is one Hsync
period. This register defines the number of edges that will be
filtered after Vsync on a composite sync.
The default is 0.
14
7–6
Output Drive
The two bits select the drive strength for the high speed digital
outputs (all data output and clock output pins). Higher drive
strength results in faster rise/fall times, and in general makes it
easier to capture data. Lower drive strength results in slower
rise/fall times and helps reduce EMI and digitally generated
power supply noise.
7–0
Pre-Coast
Table XXIX. Output Drive Strength Settings
Bit 7
Bit 6
Result
1
0
0
X
1
0
High drive strength
Medium drive strength
Low drive strength
The default for this register is 11, high drive strength. (This option works on
both the analog and digital interfaces.)
14
Bits that select the analog bandwidth.
5
Programmable Analog Bandwidth
Table XXX. Analog Bandwidth Control
Bit 5
Analog Bandwidth
0
1
10 MHz
300 MHz
14
A control bit for the inversion of the output data clock (Pin 85).
This function works only for the digital interface. When not
inverted, data is output on the falling edge of the data clock.
See the timing diagrams, Figures 14 and 15, to see how this
affects timing.
4
Clk Inv
Data Output Clock Invert
Table XXXI. Clock Output Invert Settings
Clk Inv
Function
0
1
Not inverted
Inverted
The default for this register is 0 (not inverted).
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| AD9883ABST-RL140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
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| AD9883AKST-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9882/PCB | 制造商:Analog Devices 功能描述:DUAL INTRFC FOR FLAT PNL DISPLAY 100LQFP - Bulk |
| AD9882A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882AKSTZ-100 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9882AKSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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