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參數(shù)資料
| 型號： | AD9882 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | 雙接口的平板顯示器 |
| 文件頁數(shù)： | 26/36頁 |
| 文件大小： | 370K |
| 代理商： | AD9882 |
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REV. A
–26–
AD9882
HSYNC OUTPUT PULSEWIDTH
07
7–0
Hsync Output Pulsewidth
An 8-bit register that sets the duration of the Hsync output pulse.
The leading edge of the Hsync output is triggered by the internally
generated, phase adjusted PLL feedback clock. The AD9882
then counts a number of pixel clocks equal to the value in this
register minus one. This triggers the trailing edge of the Hsync
output, which is also phase adjusted.
INPUT GAIN
08
7–0
An 8-bit word that sets the gain of the RED channel. The AD9882
can accommodate input signals with a full-scale range of between
0.5 V and 1.0 V p-p. Setting REDGAIN to 255 corresponds to
an input range of 1.0 V. A REDGAIN of 0 establishes an input
range of 0.5 V. Note that INCREASING REDGAIN results in
the picture having LESS CONTRAST (the input signal uses
fewer of the available converter codes). See Figure 2.
09
7–0
GREENGAIN GREEN Gain
An 8-bit word that sets the gain of the GREEN channel. See
REDGAIN (08).
0A
7–0
BLUEGAIN
BLUE Gain
An 8-bit word that sets the gain of the BLUE channel. See
REDGAIN (08).
REDGAIN
RED Gain
INPUT OFFSET
0B
7–1
A 7-bit offset binary word that sets the dc offset of the RED
channel. One LSB of offset adjustment equals approximately one
LSB change in the ADC offset. Therefore, the absolute magni-
tude of the offset adjustment scales as the gain of the channel is
changed. A nominal setting of 64 results in the channel nominally
clamping the back porch (during the clamping interval) to code 00.
An offset setting of 127 results in the channel clamping to code
63 of the ADC. An offset setting of 0 clamps to code
–
64 (off the
bottom of the range). Increasing the value of RED offset
DECREASES the brightness of the channel.
0C
7–1
GREEN Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the GREEN
channel. See REDOFST (0B).
0D
7–1
BLUE Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the BLUE
channel. See REDOFST (0B).
0E
7–0
Sync Separator Threshold
This register is used to set the responsiveness of the sync separator.
It sets how many internal 5 MHz clock periods the sync separa-
tor must count to before toggling high or low. It works like a
low-pass filter to ignore Hsync pulses in order to extract the
Vsync signal. This register should be set to some number greater
than the maximum Hsync pulsewidth. Note: the sync separator
threshold uses an internal dedicated clock with a frequency of
approximately 5 MHz.
The default for this register is 20H.
RED Channel Offset Adjust
0F
This register allows the comparator threshold of the Sync-on-Green
slicer to be adjusted. This register adjusts it in steps of 10 mV,
with the minimum setting equaling 10 mV and the maximum
setting equaling 330 mV.
The default setting is 15 decimal and corresponds to a threshold
value of 170 mV.
0F
2
AIO
Active Interface Override
This bit is used to override the automatic interface selection
(Bit 3 in Register 15H). To override, set this bit to logic 1. When
overriding, the active interface is set via Bit 1 in this register.
7–3
Sync-on-Green Slicer Threshold
Table XII. Active Interface Override Settings
AIO
Result
0
1
Autodetermine the active interface.
Override, Bit 1 determines the active interface.
The default for this register is 0.
0F
This bit is used under two conditions. It is used to select the active
interface when the override bit is set (Register 0FH, Bit 2).
Alternatively, it is used to determine the active interface when
not overriding but both interfaces are detected.
1
AIS
Active Interface Select
Table XIII. Active Interface Select Settings
AIS
Result
0
1
Analog interface
Digital interface
The default for this register is 0.
10
This register is used to override the internal circuitry that determines
the polarity of the Hsync signal going into the PLL.
7
Hsync Input Polarity Override
Table XIV. Hsync Input Polarity Override Settings
Override Bit
Result
0
1
Hsync polarity determined by chip.
Hsync polarity determined by Register 10H,
Bit 6.
The default for Hsync polarity override is 0. (Polarity determined by chip.)
10
A bit that must be set to indicate the polarity of the Hsync signal
that is applied to the PLL Hsync input.
6
HSPOL
Hsync Input Polarity
Table XV. Hsync Input Polarity Settings
HSPOL
Function
0
1
Active LOW
Active HIGH
Active LOW means the leading edge of the Hsync pulse is negative-
going. All timing is based on the leading edge of Hsync, which
is the FALLING edge. The rising edge has no effect.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9882/PCB | 制造商:Analog Devices 功能描述:DUAL INTRFC FOR FLAT PNL DISPLAY 100LQFP - Bulk |
| AD9882A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882AKSTZ-100 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9882AKSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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