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參數資料
| 型號： | AD9882 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | 雙接口的平板顯示器 |
| 文件頁數： | 30/36頁 |
| 文件大小： | 370K |
| 代理商： | AD9882 |
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REV. A
–30–
AD9882
15
This bit is used to indicate which interface should be active, analog
or digital. It checks for activity on the analog interface and for
activity on the digital interface, then determines which should be
active according to Table XLI. Specifically, analog interface detec-
tion is determined by OR-ing Bits 7, 6, and 5 in this register. Digital
interface detection is determined by Bit 4 in this register. If both
interfaces are detected, the user can determine which has priority
via Bit 1 in Register 0FH. The user can override this function
via Bit 2 in Register 0FH. If the override bit is set to logic 1, then
this bit will be forced to the same state as Bit 1 in Register 0FH.
3
Active Interface
Table XLI. Active Interface Results
Bits 7, 6, or 5
(Analog
Detection)
Bit 4
(Digital
Detection)
Override
AI
0
0
0
Soft
Power-Down
(Seek Mode)
1
0
Bit 1 in 0FH
Bit 1 in 0FH
0
1
1
X
1
0
1
X
0
0
0
1
AI = 0 means analog interface
AI = 1 means digital interface
The override bit is in Register 0FH, Bit 2.
16
This bit indicates which Hsync input source is being used by the
PLL (Hsync input or Sync-on-Green). Bits 6 and 7 in Register
15H determine which source is used. If both Hsync and SOG
are detected, the user can determine which has priority via Bit 3
in Register 10H. The user can override this function via Bit 4
in Register 10H. If the override bit is set to logic 1, then this
bit will be forced to the same state as Bit 3 in Register 10H.
7
AHS
Active Hsync
Table XLII. Active Hsync Results
Hsync Detect SOG Detect
Register 15H
Bit 7
Override
AHS
Register 16H
Bit 7
Register 15H Register 10H
Bit 6
Bit 4
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
Bit 3 in 10H
1
0
Bit 3 in 10H
Bit 3 in 10H
AHS = 0 means use the Hsync pin input for Hsync
AHS = 1 means use the SOG pin input for Hsync
The override bit is in Register 10H, Bit 4.
16
This bit reports the status of the Hsync input polarity detection
circuit. It can be used to determine the polarity of the Hsync
input. The detection circuit
’
s location is shown in the Sync
Processing Block Diagram, Figure 18.
6
Detected Hsync Input Polarity Status
Table XLIII. Detected Hsync Input Polarity Status
Hsync Polarity
Status
Result
0
1
Hsync polarity is negative/active low.
Hsync polarity is positive/active high.
16
This bit indicates which Vsync source is being used for the analog
interface: the Vsync input or output from the sync separator.
If the override bit (10H, Bit 1) is set to logic 1, then this bit will be
forced to the same state as Bit 0 in Register 10H.
5
AVS
Active Vsync
Table XLIV. Active Vsync Results
Vsync Detect
Register 16H
Bit 5
Override
Register 10H
Bit 1
AVS
0
1
X
0
0
1
0
1
Bit 0 in 10H
AVS = 0 means Vsync input
AVS = 1 means Sync separator
The override bit is in Register 10H, Bit 1.
16
This bit reports the status of the Vsync output polarity detection
circuit. It can be used to determine the polarity of the Vsync
output. The detection circuit
’
s location is shown in the Sync
Processing Block Diagram, Figure 18.
4
Detected Vsync Output Polarity Status
Table XLV. Detected Vsync Input Polarity Status
Vsync Polarity Status
Result
0
1
Vsync polarity is active high.
Vsync polarity is active low.
16
This bit reports the status of the coast input polarity detection
circuit. The detection circuit
’
s location is shown in the Sync
Processing Block Diagram, Figure 18. This bit only applies to
the internal Coast and does not apply when Coast is disabled.
3
Detected Coast Polarity Status
Table XLVI. Detected Coast Input Polarity Status
Hsync Polarity
Status
Result
0
1
Coast polarity is negative/active low.
Coast polarity is positive/active high.
16
This bit reports wherever HDCP keys are detected.
2
Key Read Verification
Table XLVII. Key Read Verification
Detect
Function
0
1
Not detected
Detected
1B
The MDA and MCL three-state feature allows the EEPROM to
be programmed in-circuit. The MDA/MCL port must be three-
stated before attempting to program the EEPROM using an
external master. The keys will be stored in an I
2
C compatible
3.3 V serial EEPROM of at least 512 bytes. The EEPROM
should have a device address of A0H.
7
MDA and MCL Three-State
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9882/PCB | 制造商:Analog Devices 功能描述:DUAL INTRFC FOR FLAT PNL DISPLAY 100LQFP - Bulk |
| AD9882A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882AKSTZ-100 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9882AKSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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