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參數資料
| 型號： | AD9882 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | 雙接口的平板顯示器 |
| 文件頁數： | 25/36頁 |
| 文件大小： | 370K |
| 代理商： | AD9882 |
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REV. A
AD9882
–25–
2-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
00
7–0
Chip Revision
An 8-bit register that represents the silicon revision. Revision 0
= 0000 0000.
PLL DIVIDER CONTROL
01
7–0
PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
The PLL derives a pixel clock from the incoming Hsync signal.
The pixel clock frequency is then divided by an integer value,
such that the output is phase-locked to Hsync. This PLLDIV
value determines the number of pixel times (pixels plus horizontal
blanking overhead) per line. This is typically 20% to 30% more
than the number of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios from
221 to 4095. The higher the value loaded in this register, the
higher the resulting clock frequency with respect to a fixed Hsync
frequency.
VESA has established some standard timing specifications that will
assist in determining the value for PLLDIV as a function of the
horizontal and vertical display resolution and frame rate
(Table VII). However, many computer systems do not conform
precisely to the recommendations, and these numbers should be
used only as a guide. The display system manufacturer should
provide automatic or manual means for optimizing PLLDIV.
An incorrectly set PLLDIV will usually produce one or more
vertical noise bars on the display. The greater the error, the
greater the number of bars produced.
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69H, PLLDIVL = DxH).
The AD9882 updates the full divide ratio only when the LSBs are
changed. Writing to this register by itself will not trigger an update.
02
7–4
PLL Divide Ratio LSBs
The four least significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69H, PLLDIVL = DxH).
The AD9882 updates the full divide ratio only when this register
is written.
03
7–6
VCO Range Select
Two bits that establish the operating range of the clock generator.
VCORNGE must be set to correspond with the desired operating
frequency (incoming pixel rate).
The PLL VCO gives the best jitter performance while operating
at high frequencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL VCO actually
operates at a higher frequency but then divides down the clock
rate afterward. Table X shows the pixel rates for each VCO range
setting. The PLL output divisor is automatically selected with
the VCO range setting.
Table X. VCO Ranges
VCORNGE
Pixel Rate Range
00
01
10
12
–
41
41
–
82
82
–
140
The power-up default value is VCORNGE = 01.
03
Three bits that establish the current driving the loop filter in the
clock generator.
5–3
CURRENT
Charge Pump Current
Table XI. Charge Pump Currents
Charge Pump
Current (
m
A)
50
100
150
250
350
500
750
1500
000
001
010
011
100
101
110
111
CHARGE PUMP must be set to correspond with the desired
operating frequency (incoming pixel rate). See Table XI for the
charge pump current for each register setting.
The power-up default value is CURRENT = 001.
04
7–3
Phase Adjust
A 5-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25
∞
shift in
sampling phase.
The power-up default Phase adjust value is 10H.
CLAMP TIMING
05
7–0
An 8-bit register that sets the position of the internally gener-
ated clamp.
When CLAMP FUNCTION (Register 11H, Bit 7) = 0, a clamp
signal is generated internally at a position established by the
clamp placement and for a duration set by the clamp duration.
Clamping is started (Clamp Placement) an integral number of
pixel periods after the trailing edge of Hsync. The clamp place-
ment may be programmed to any value between 1 and 255.
The clamp should be placed during a time that the input signal
presents a stable black-level reference, usually the back porch
period between Hsync and the image.
When CLAMP FUNCTION = 1, this register is ignored.
06
7–0
Clamp Duration
An 8-bit register that sets the duration of the internally gener-
ated clamp.
For the best results, the clamp duration should be set to include
the majority of the black reference signal time that follows the
Hsync signal trailing edge. Insufficient clamping time can produce
brightness changes at the top of the screen and a slow recovery from
large changes in the Average Picture Level (APL) or brightness.
When CLAMP FUNCTION = 1, this register is ignored.
Clamp Placement
相關PDF資料 |
PDF描述 |
|---|---|
| AD9883ABST-RL140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKST-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKST-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883A | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883ABST-RL110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9882/PCB | 制造商:Analog Devices 功能描述:DUAL INTRFC FOR FLAT PNL DISPLAY 100LQFP - Bulk |
| AD9882A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882AKSTZ-100 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9882AKSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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