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參數(shù)資料
| 型號： | ADSP-21MOD980N-000 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CAP 27PF 100V 10% X7R AXIAL BULK M-MIL-PRF-39014 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA352 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-352 |
| 文件頁數(shù)： | 15/42頁 |
| 文件大小： | 566K |
| 代理商： | ADSP-21MOD980N-000 |
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15
REV. PrB
6/2001
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
IDMA PORT BOOTING
The ADSP-21mod980N boots programs through its Inter-
nal DMA port.When Mode C = 1, Mode B = 0, and Mode
A = 1, the ADSP-21mod980N boots from the IDMA port.
IDMA feature can load as much on-chip memory as
desired. Program execution is held off until on-chip pro-
gram memory location 0 is written to.
FLAG I/O PINS
Each modem processor has eight general purpose program-
mable input/output flag pins. They are controlled by two
memory mapped registers. The PFTYPE register deter-
mines the direction, 1 = output and 0 = input. The
PFDATA register is used to read and write the values on the
pins. Data being read from a pin configured as an input is
synchronized to the ADSP-21mod980N
’
s clock. Bits that
are programmed as outputs will read the value being out-
put. The PF pins default to input during RESET.
Note: Pins PF0, PF1, and PF2 are also used for device con-
figuration during RESET. Since they are multiplexed
within the ADSP-21mod980N, PF[2:0] should be config-
ured as an output for only one processor at a time.
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