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參數(shù)資料
| 型號： | ADSP-21MOD980N-000 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CAP 27PF 100V 10% X7R AXIAL BULK M-MIL-PRF-39014 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA352 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-352 |
| 文件頁數(shù)： | 9/42頁 |
| 文件大小： | 566K |
| 代理商： | ADSP-21MOD980N-000 |
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9
REV. PrB
6/2001
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICA L DATA
CLOCK SIGNALS
The ADSP-21mod980N is clocked by a TTL-compatible
clock signal that runs at half the instruction rate; a 40 MHz
input clock yields a 12.5 ns processor cycle, which is equiv-
alent to 80 MHz. Normally, instructions are executed in a
single processor cycle. All device timing is relative to the
internal instruction clock rate, which is indicated by the
CLKOUT signal when enabled. The clock input signal is
connected to the processor
’
s CLKIN input.
The CLKIN input cannot be halted, changed during oper-
ation, or operated below the specified frequency during
normal operation. The only exception is while the processor
is in the power down state. For additional information, refer
to Chapter 9, ADSP-2100 Family User
’
s Manual for a
detailed explanation of this power down feature.
Figure 3. Multichannel Modem Configuration
SPORT
21mod980N
ST/CNTL IDMA
SPORT
21mod980N
ST/CNTL IDMA
21mod980N
ST/CNTL IDMA
T1/E1
LINE
INTERFACE
SPORT
T1/E1
LINE
INTERFACE
T1/E1
LINE
INTERFACE
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