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參數資料
| 型號： | ADSP-21MOD980N-000 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | CAP 27PF 100V 10% X7R AXIAL BULK M-MIL-PRF-39014 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA352 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-352 |
| 文件頁數： | 24/42頁 |
| 文件大小： | 566K |
| 代理商： | ADSP-21MOD980N-000 |
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24
6/2001
REV. PrB
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
TIMING SPECIFICATIONS
PRELIMINARY TECHNICAL DATA
This section contains timing information for the DSP
’
s
external signals.
General Notes
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of oth-
ers. While addition or subtraction would yield meaningful
results for an individual device, the values given in this data
sheet reflect statistical variations and worst cases. Conse-
quently, you cannot meaningfully add up parameters to
derive longer times.
Timing Notes
Switching characteristics specify how the processor changes
its signals. You have no control over this timing
—
circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics
tell you what the processor will do in a given circumstance.
You can also use switching characteristics to ensure that any
timing requirement of a device connected to the processor
(such as memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for
a read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
Frequency Dependency For Timing Specifications
t
CK
is defined as 0.5 t
CKI
. The ADSP-21mod980N uses an
input clock with a frequency equal to half the instruction
rate. For example, a 40 MHz input clock (which is equiva-
lent to 25 ns) yields a 12.5 ns processor cycle (equivalent to
80 MHz). t
CK
values within the range of 0.5 t
CKI
period
should be substituted for all relevant timing parameters to
obtain the specification value.
Example: t
CKH
= 0.5 t
CK
–
2 ns = 0.5 (12.5 ns)
–
2 ns = 4.25
ns
Output Drive Currents
Figure 14
shows typical I-V characteristics for the output
drivers on the ADSP-21mod980N. The curves represent
the current drive capability of the output drivers as a func-
tion of output voltage
Capacitive Loading
Figure 16
and
Figure 17
show the capacitive loading char-
acteristics of the ADSP-21mod980N.
Figure 17. Typical Output Rise Time vs.Load Capacitance
(at Maximum Ambient Operating Temperature)
Figure 18. Typical Output Valid Delay or Hold vs.Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
C
L
- pF
R
30
300
0
50
100
150
200
250
25
15
10
5
0
20
T = 85 C
V
DD
= 0V TO 2.0V
C
L
- pF
14
0
V
50
100
150
250
200
12
4
2
-2
10
8
NOMINAL
16
18
6
-4
-6
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