- 您現在的位置：買賣IC網 > PDF目錄374037 > ADSP-BF531 (Analog Devices, Inc.) Blackfin Embedded Processor PDF資料下載
參數資料
| 型號： | ADSP-BF531 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Blackfin Embedded Processor |
| 中文描述： | Blackfin嵌入式處理器 |
| 文件頁數： | 8/56頁 |
| 文件大小： | 671K |
| 代理商： | ADSP-BF531 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
Rev. 0
|
Page 8 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF531/2/3 processor has multiple, independent
DMA controllers that support automated data transfers with
minimal overhead for the processor core. DMA transfers can
occur between the ADSP-BF531/2/3 processor's internal memo-
ries and any of its DMA-capable peripherals. Additionally,
DMA transfers can be accomplished between any of the DMA-
capable peripherals and external devices connected to the exter-
nal memory interfaces, including the SDRAM controller and
the asynchronous memory controller. DMA-capable peripher-
als include the SPORTs, SPI port, UART, and PPI. Each
individual DMA-capable peripheral has at least one dedicated
DMA channel.
The ADSP-BF531/2/3 processor DMA controller supports both
1-dimensional (1D) and 2-dimensional (2D) DMA transfers.
DMA transfer initialization can be implemented from registers
or from sets of parameters called descriptor blocks.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
Examples of DMA types supported by the ADSP-BF531/2/3
processor DMA controller include:
A single, linear buffer that stops upon completion
A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
1-D or 2-D DMA using a linked list of descriptors
2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the ADSP-BF531/2/3 processor system.
This enables transfers of blocks of data between any of the
memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptor
based methodology or by a standard register based autobuffer
mechanism.
REAL-TIME CLOCK
The ADSP-BF531/2/3 processor Real-Time Clock (RTC) pro-
vides a robust set of digital watch features, including current
time, stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the ADSP-BF531/2/3 processor.
The RTC peripheral has dedicated power supply pins so that it
can remain powered up and clocked even when the rest of the
processor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per sec-
ond, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a pro-
grammed alarm time.
The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60-second counter, a 60-minute
counter, a 24-hour counter, and a 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like other peripherals, the RTC can wake up the processor from
Sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from Deep Sleep mode, and wake up the on-chip internal volt-
age regulator from a powered-down state.
Connect RTC pins RTXI and RTXO with external components
as shown in
Figure 6
.
Figure 6. External Components for RTC
RTXO
C1
C2
X1
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10 M OHM
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
RTXI
R1
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-BF531SBBC400 | Metal Connector Backshell |
| ADSP-BF531SBBZ400 | Blackfin Embedded Processor |
| ADSP-BF531SBST400 | Circular Connector Series:97 |
| ADSP-BF532 | Blackfin Embedded Processor |
| ADSP-BF532SBBC400 | Blackfin Embedded Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-BF531SBB400 | 功能描述:IC DSP CTLR 16BIT 400MHZ 169-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSPBF531SBBC400 | 制造商:Analog Devices 功能描述: |
| ADSP-BF531SBBC400 | 功能描述:IC DSP CTLR 16B 400MHZ 160MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF531SBBC-400X | 制造商:Analog Devices 功能描述: |
| ADSP-BF531SBBC-ENG | 制造商:Analog Devices 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。