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參數(shù)資料
| 型號： | ADUC824 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| 中文描述： | MicroConverter的，雙通道ADC的16-/24-Bit與嵌入式閃存MCU |
| 文件頁數(shù)： | 41/68頁 |
| 文件大小： | 1060K |
| 代理商： | ADUC824 |
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REV. B
ADuC824
–41–
USER INTERFACE TO OTHER ON-CHIP ADuC824
PERIPHERALS
The following section gives a brief overview of the various peripher-
als also available on-chip. A summary of the SFRs used to control
and configure these peripherals is also given.
DAC
The ADuC824 incorporates a 12-bit, voltage output DAC on-chip.
It has a rail-to-rail voltage output buffer capable of driving
10 k
/100 pF. It has two selectable ranges, 0 V to V
REF
(the inter-
nal bandgap 2.5 V reference) and 0 V to AV
DD
. It can operate in
12-bit or 8-bit mode. The DAC has a control register, DACCON,
and two data registers, DACH/L. The DAC output can be
programmed to appear at Pin 3 or Pin 12. It should be noted
that in 12-bit mode, the DAC voltage output will be updated as
soon as the DACL data SFR has been written; therefore, the DAC
data register should be updated as DACH first followed by DACL.
DACH/L
Function
SFR Address
DAC Data Register
DAC Data Registers, written by user to update the DAC output.
DACL (DAC Data Low Byte) –>FBH
DACH (DAC Data High Byte) –>FCH
00H
No
Power-On Default Value
Bit Addressable
–>Both Registers
–>Both Registers
The 12-bit DAC data should be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower
nibble of DACH contains the upper four bits.
DACCON
SFR Address
Power-On Default Value
Bit Addressable
DAC Control Register
FDH
00H
No
Table XVI. DACCON SFR Bit Designations
Bit
Name
Description
7
6
5
4
—
—
—
DACPIN
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
DAC Output Pin Select
Set
by user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared
by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
DAC 8-Bit Mode Bit
Set
by user to enable 8-bit DAC operation. In this mode the 8-bits in DACL SFR are routed to the
8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero.
Cleared
by user to operate the DAC in its normal 12-bit mode of operation.
DAC Output Range Bit
Set
by user to configure DAC range of 0 –AV
.
Cleared
by user to configure DAC range 0 – 2.5 V.
DAC Clear Bit
Set
to ‘1’ by user to enable normal DAC operation.
Cleared
to ‘0’ by used to reset DAC data registers DAC1/H to zero.
DAC Enable Bit
Set
to ‘1’ by user to enable normal DAC operation.
Cleared
to ‘0’ by used to power-down the DAC.
3
DAC8
2
DACRN
1
DACCLR
0
DACEN
—
—
—
DACPIN
DAC8
DACRN
DACCLR
DACEN
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