- 您現在的位置：買賣IC網 > PDF目錄374039 > ADUC824 (Analog Devices, Inc.) MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU PDF資料下載
參數資料
| 型號： | ADUC824 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| 中文描述： | MicroConverter的，雙通道ADC的16-/24-Bit與嵌入式閃存MCU |
| 文件頁數： | 64/68頁 |
| 文件大?。?/td> | 1060K |
| 代理商： | ADUC824 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當前第64頁第65頁第66頁第67頁第68頁
REV. B
ADuC824
–64–
As an alternative to providing two separate power supplies, AV
DD
quiet by placing a small series resistor and/or ferrite bead between
it and DV
DD
, and then decoupling AV
DD
separately to ground. An
example of this configuration is shown in Figure 51. With this
configuration other analog circuitry (such as op amps, voltage
reference, etc.) can be powered from the AV
DD
supply line as well.
DV
DD
48
34
20
ADuC824
5
6
AGND
AV
DD
0.1 F
10 F
DGND
35
21
47
0.1 F
–
+
DIGITAL SUPPLY
10 F
1.6
BEAD
Figure 51. External Single Supply Connections
Notice that in both Figure 50 and Figure 51, a large value (10
μ
F)
reservoir capacitor sits on DV
DD
and a separate 10
μ
F capacitor
sits on AV
DD
. Also, local small-value (0.1
μ
F) capacitors are
located at each VDD pin of the chip. As per standard design prac-
tice, be sure to include all of these capacitors, and ensure the
smaller capacitors are closest to each AV
DD
pin with trace lengths
as short as possible. Connect the ground terminal of each of these
capacitors directly to the underlying ground plane. Finally, it
should also be noticed that, at all times, the analog and digital
ground pins on the ADuC824 should be referenced to the same
system ground reference point.
Power Consumption
The “CORE” values given represent the current drawn by DV
DD
,
while the rest (“ADC,” and “DAC”) are pulled by the AV
DD
pin
and can be disabled in software when not in use. The other
on-chip peripherals (watchdog timer, power supply monitor, etc.)
consume negligible current and are therefore lumped in with the
“CORE” operating current here. Of course, the user must add
any currents sourced by the parallel and serial I/O pins, and that
sourced by the DAC, in order to determine the total current
needed at the ADuC824’s supply pins. Also, current draw from
the DVDD supply will increase by approximately 5 mA during
Flash/EE erase and program cycles
Power-Saving Modes
Setting the Idle and Power-Down Mode bits, PCON.0 and
PCON.1 respectively, in the PCON SFR described in Table II,
allows the chip to be switched from normal mode into idle mode,
and also into full power-down mode.
In idle mode, the oscillator continues to run, but the core clock
generated from the PLL is halted. The on-chip peripherals con-
tinue to receive the clock, and remain functional. The CPU status
is preserved with the stack pointer, program counter, and all other
internal registers maintain their data during idle mode. Port pins
and DAC output pins also retain their states, and ALE and
PSEN
outputs go high in this mode. The chip will recover from
idle mode upon receiving any enabled interrupt, or on receiving
a hardware reset.
In power-down mode, both the PLL and the clock to the core
are stopped. The on-chip oscillator can be halted or can continue
to oscillate depending on the state of the oscillator power-down
bit (OSC_PD) in the PLLCON SFR. The TIC, being driven
directly from the oscillator, can also be enabled during power-
down. All other on-chip peripherals however, are shut down.
Port pins retain their logic levels in this mode, but the DAC output
goes to a high-impedance state (three-state) while ALE and
PSEN
outputs are held low. During full power-down mode,
the ADuC824 consumes a total of 5
μ
A typically. There are five
ways of terminating power-down mode:
Asserting the RESET Pin (#15)
Returns to normal mode all registers are set to their default state
and program execution starts at the reset vector once the Reset
pin is de-asserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated and the CPU services the TIC
interrupt, the RETI at the end of the TIC Interrupt Service
Routine will return the core to the instruction after that which
enabled power down.
I
2
C or SPI Interrupt
Power-down mode is terminated and the CPU services the I
2
C/
SPI interrupt. The RETI at the end of the ISR will return the
core to the instruction after that which enabled power down. It
should be noted that the I
2
C/SPI power down interrupt enable
bit (SERIPD) in the PCON SFR must first be set to allow this
mode of operation.
INT0
Interrupt
Power-down mode is terminated and the CPU services the
INT0
interrupt. The RETI at the end of the ISR will return the
core to the instruction after that which enabled power-down. It
should be noted that the
INT0
power-down interrupt enable bit
(INT0PD) in the PCON SFR must first be set to allow this
mode of operation.
Grounding and Board Layout Recommendations
As with all high resolution data converters, special attention must
be paid to grounding and PC board layout of ADuC824-based
designs in order to achieve optimum performance from the ADCs
and DAC.
Although the ADuC824 has separate pins for analog and digital
ground (AGND and DGND), the user must not tie these to two
separate ground planes unless the two ground planes are con-
nected together very close to the ADuC824, as illustrated in the
simplified example of Figure 52a. In systems where digital and
analog ground planes are connected together somewhere else
(at the system’s power supply for example), they cannot be con-
nected again near the ADuC824 since a ground loop would result.
In these cases, tie the ADuC824’s AGND and DGND pins all
to the analog ground plane, as illustrated in Figure 52b. In systems
with only one ground plane, ensure that the digital and analog
components are physically separated onto separate halves of the
board such that digital return currents do not flow near analog
circuitry and vice versa. The ADuC824 can then be placed between
the digital and analog sections, as illustrated in Figure 52c.
相關PDF資料 |
PDF描述 |
|---|---|
| ADUC824BS | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| ADUC831 | LJT 6C 6#22D PIN RECP |
| ADUC831BCP | Circular Connector; No. of Contacts:6; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:9; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:9-35 |
| ADUC831BS | MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU |
| ADUC836 | MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADUC824BCP | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 56-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 8KB FLASH 12.58MHZ 3.3/5V 56LFCSP - Bulk |
| ADUC824BCP-REEL | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 56-Pin LFCSP EP T/R |
| ADUC824BCPZ | 功能描述:IC MCU 8K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數:16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數據轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC824BS | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 8KB FLASH 12.58MHZ 3.3/5V 52MQFP - Bulk 制造商:Analog Devices 功能描述:8BIT MCU +24BIT ADC LQFP52 824 |
| ADUC824BS-DEN | 制造商:Analog Devices 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。