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參數資料
| 型號： | ADUC824 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| 中文描述： | MicroConverter的，雙通道ADC的16-/24-Bit與嵌入式閃存MCU |
| 文件頁數： | 49/68頁 |
| 文件大小： | 1060K |
| 代理商： | ADUC824 |
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REV. B
ADuC824
–49–
SPIDAT
Function
SPI Data Register
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user
code to read data just received by the SPI interface.
F7H
00H
No
SFR Address
Power-On Default Value
Bit Addressable
Using the SPI Interface
Depending on the configuration of the bits in the SPICON SFR
shown in Table XIX, the ADuC824 SPI interface will transmit
or receive data in a number of possible modes. Figure 33 shows
all possible ADuC824 SPI configurations and the timing rela-
tionships and synchronization between the signals involved.
Also shown in this figure is the SPI interrupt bit (ISPI) and how
it is triggered at the end of each byte-wide communication.
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
MSB BIT 6 BIT 5
BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
ISPI FLAG
Figure 33. SPI Timing, All Modes
SPI Interface
—
Master Mode
In master mode, the SCLOCK pin is always an output and gener-
ates a burst of eight clocks whenever user code writes to the
SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the
SS
pin is not used in master mode. If the ADuC824 needs to
assert the
SS
pin on an external slave device, a Port digital output
pin should be used.
In master mode a byte transmission or reception is initiated
by a write to SPIDAT. Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.
With each SCLOCK period a data bit is also sampled via MISO.
After eight clocks, the transmitted byte will have been completely
transmitted and the input byte will be waiting in the input shift
register. The ISPI flag will be set automatically and an interrupt
will occur if enabled. The value in the shift register will be latched
into SPIDAT.
SPI Interface
—
Slave Mode
In slave mode the SCLOCK is an input. The
SS
pin must
also be driven low externally during the byte communication.
Transmission is also initiated by a write to SPIDAT. In slave
mode, a data bit is transmitted via MISO and a data bit is received
via MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte will have been completely transmitted and the
input byte will be waiting in the input shift register. The ISPI flag
will be set automatically and an interrupt will occur if enabled.
The value in the shift register will be latched into SPIDAT only
when the transmission/reception of a byte has been completed.
The end of transmission occurs after the eighth clock has been
received, if CPHA = 1 or when
SS
returns high if CPHA = 0.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADUC824BCP | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 56-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 8KB FLASH 12.58MHZ 3.3/5V 56LFCSP - Bulk |
| ADUC824BCP-REEL | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 56-Pin LFCSP EP T/R |
| ADUC824BCPZ | 功能描述:IC MCU 8K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數:16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數據轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC824BS | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 8KB FLASH 12.58MHZ 3.3/5V 52MQFP - Bulk 制造商:Analog Devices 功能描述:8BIT MCU +24BIT ADC LQFP52 824 |
| ADUC824BS-DEN | 制造商:Analog Devices 功能描述: |
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