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參數資料
型號: ADUC824
廠商: Analog Devices, Inc.
元件分類: 串行ADC
英文描述: MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU
中文描述: MicroConverter的,雙通道ADC的16-/24-Bit與嵌入式閃存MCU
文件頁數: 53/68頁
文件大小: 1060K
代理商: ADUC824
REV. B
ADuC824
–53–
TCON
SFR Address
Power-On Default Value
Bit Addressable
Timer/Counter 0 and 1 Control Register
88H
00H
Yes
1
F
T
1
R
T
0
F
T
0
R
T
1
E
I
*
1
T
I
*
0
E
I
*
0
T
I
*
*
These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external
INT0
and
INT1
interrupt pins.
Table XXIV. TCON SFR Bit Designations
Bit
Name
Description
7
TF1
Timer 1 Overflow Flag
Set
by hardware on a timer/counter 1 overflow.
Cleared
by hardware when the Program Counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit
Set
by user to turn on timer/counter 1.
Cleared
by user to turn off timer/counter 1.
Timer 0 Overflow Flag
Set
by hardware on a timer/counter 0 overflow.
Cleared
by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit
Set
by user to turn on timer/counter 0.
Cleared
by user to turn off timer/counter 0.
External Interrupt 1 (
INT1
) Flag
Set
by hardware by a falling edge or zero level being applied to external interrupt pin
INT1
, depending
on bit IT1 state.
Cleared
by hardware when the when the PC vectors to the interrupt service routine only if the interrupt
was transition-activated. If level-activated, the external requesting source controls the request flag,
rather than the on-chip hardware.
External Interrupt 1 (IE1) Trigger Type
Set
by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared
by software to specify level-sensitive detection (i.e., zero level).
External Interrupt 0 (
INT0
) Flag
Set
by hardware by a falling edge or zero level being applied to external interrupt pin
INT0
, depending
on bit IT0 state.
Cleared
by hardware when the PC vectors to the interrupt service routine only if the interrupt was
transition-activated. If level-activated, the external requesting source controls the request flag,
rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type
Set
by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared
by software to specify level-sensitive detection (i.e., zero level).
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register
depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8Chex, 8Ahex respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8Dhex, 8Bhex respectively.
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參數描述
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ADUC824BCPZ 功能描述:IC MCU 8K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:MicroConverter® ADuC8xx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA,UART/USART 外圍設備:欠壓檢測/復位,LED,POR,PWM,WDT 輸入/輸出數:16 程序存儲器容量:4KB(4K x 8) 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數據轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC(0.295",7.50mm 寬) 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND
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ADUC824BS-DEN 制造商:Analog Devices 功能描述:
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