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參數資料
型號: ADV7320
廠商: Analog Devices, Inc.
英文描述: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
中文描述: 多格式視頻編碼器216兆赫六噪聲整形的12位DAC
文件頁數: 18/88頁
文件大小: 1002K
代理商: ADV7320
ADV7320/ADV7321
Pin No.
62–58,
55–51
33
Rev. 0 | Page 18 of 88
Mnemonic
S9 to S0
Input/Output Description
I
SD or Progressive Scan/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up
on Pin S0. For 8-bit data input, LSB is set up on S2.
This input resets the on-chip timing generator and sets the ADV7320/ADV7321 into default
register setting. RESET is an active low signal.
A 3040 resistor must be connected from this pin to AGND and is used to control the
amplitudes of the DAC outputs.
I
2
C Port Serial Interface Clock Input.
I
2
C Port Serial Data Input/Output.
TTL Address Input. This signal sets up the LSB of the I
2
C address. When this pin is tied low, the
I
2
C filter is activated, which reduces noise on the I
2
C interface.
Power Supply for Digital Inputs and Outputs.
Digital Power Supply.
Analog Power Supply.
Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
External Loop Filter for the Internal PLL.
Multifunctional Input. Real-time control (RTC) input, timing reset input, subcarrier reset input.
This input pin must be tied high (V
DD_IO
) for the ADV7320/ADV7321 to interface over the I
2
C port.
Digital Input/Output Ground.
RESET
I
47, 35
R
SET1
, R
SET2
I
22
21
20
SCLK
SDA
ALSB
I
I/O
I
1
10, 56
41
46
34
31
19
64
V
DD_IO
V
DD
V
AA
V
REF
EXT_LF
RTC_SCR_TR I
I
2
C
GND_IO
P
P
P
I/O
I
I
相關PDF資料
PDF描述
ADV7321 Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7321KSTZ Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7324 Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
ADV7324KSTZ Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
ADV7340 Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS
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