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參數(shù)資料
| 型號(hào)： | ADV7320 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁(yè)數(shù)： | 61/88頁(yè) |
| 文件大小： | 1002K |
| 代理商： | ADV7320 |
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ADV7320/ADV7321
HSYNC/VSYNC OUTPUT CONTROL
Rev. 0 | Page 61 of 88
The ADV7320/21 has the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on
P_HSYNC/P_VSYNC, outputting the respective signals on the P_HSYNC and P_VSYNC pins.
Table 36. Hsync Output Control
1
HD/ED
2
Slave Mode
(0x10, bit 2)
x
x
HD/ED
Sync Out Enable
(0x02, Bit 7)
0
0
SD
Sync Out Enable
(0x02, Bit 6)
0
1
I2C_HSYNC _gen_sel
(0x14, Bit 1)
x
x
Signal on S_HSYNC Pin
Tristate
Pipelined SD HSYNC
Duration
–
See Appendix
5—SD Timing
Modes
As per HSYNC
timing
External HSYNC
& VSYNC/Field
Mode
EAV/SAV Mode
1
x
0
Pipelined Ext HD/ED HSYNC
1
x
0
Pipelined HD/ED HSYNC
based on AV code H bit
Pipelined HD/ED HSYNC
based on horizontal counter
Same as line
blanking interval
Same as
embedded
HSYNC
x
1
x
1
______________________________
1
In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
2
ED = enhanced definition.
Table 37. VSYNC Output Control
1
HD/ED
2
Slave Mode
(0x10, Bit 2)
(0x02, Bit 7)
(0x02, Bit 6)
(0x14, Bit 2)
x
0
0
x
x
0
1
x
HD/ED
Sync out Enable
SD
Sync Out Enable
I2C_VSYNC _gen_sel
Video
Standard
x
Interlaced
Signal on
S_VSYNC Pin
Tristate
Pipelined SD
VSYNC/ field
Duration
-
See Appendix
5—SD Timing
Modes
As per Ext VSYNC
or field signal
External HSYNC
& VSYNC/Field
Mode
EAV/SAV Mode
1
x
0
x
Pipelined EXT
HD/ED VSYNC or
field signal
External pipelined
field signal based
on AV code F bit
Pipelined VSYNC
based on AV code
V bit
External pipelined
HD/ED VSYNC
based on vertical
counter
External pipelined
HD/ED VSYNC
based on vertical
counter
1
x
0
All HD interlace
standards
Field
EAV/SAV Mode
1
x
0
All HD/ED
progressive
standards
All HD/ED stan-
dards except
525p
Vertical blanking
interval
x
1
x
1
Aligned with
serration lines
x
1
x
1
525p
Vertical blanking
interval
1
In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
2
ED = enhanced definition.
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